From: Xi Ruoyao <xry111@xry111.site>
To: gcc-patches@gcc.gnu.org
Cc: chenglulu <chenglulu@loongson.cn>,
i@xen0n.name, xuchenghua@loongson.cn,
Xi Ruoyao <xry111@xry111.site>
Subject: [PATCH v2 1/6] LoongArch: Fix internal error running "gcc -march=native" on LA664
Date: Sat, 18 Nov 2023 04:43:18 +0800 [thread overview]
Message-ID: <20231117204323.453536-2-xry111@xry111.site> (raw)
In-Reply-To: <20231117204323.453536-1-xry111@xry111.site>
On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture
is guessed ISA_BASE_LA64V100. This causes a warning to be outputed:
cc1: warning: base architecture 'la64' differs from PRID preset '?'
But we've not set the "?" above in loongarch_isa_base_strings, thus it's
a nullptr and then an ICE is triggered.
Add ISA_BASE_LA64V110 to genopts and initialize
loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE.
The warning itself will be fixed later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings:
(STR_ISA_BASE_LA64V110): Add.
* config/loongarch/genopts/loongarch.opt.in:
(ISA_BASE_LA64V110): Add.
* config/loongarch/loongarch-def.c
(loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
to STR_ISA_BASE_LA64V110.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
---
gcc/config/loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-def.c | 1 +
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
5 files changed, 9 insertions(+)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index 7bc4824007e..b2070c83ed0 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -30,6 +30,7 @@ STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
+STR_ISA_BASE_LA64V110 la64v1.1
# -mfpu
OPTSTR_ISA_EXT_FPU fpu
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 00b4733d75b..b274b3fb21e 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -32,6 +32,9 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
+EnumValue
+Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110)
+
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
index 067629141b6..f22d488acb2 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -165,6 +165,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
const char*
loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
[ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
+ [ISA_BASE_LA64V110] = STR_ISA_BASE_LA64V110,
};
const char*
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index fc4f41bfc1e..114dbc692d7 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
+#define STR_ISA_BASE_LA64V110 "la64v1.1"
#define OPTSTR_ISA_EXT_FPU "fpu"
#define STR_NONE "none"
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 7f129e53ba5..350ca30d232 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -39,6 +39,9 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
+EnumValue
+Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110)
+
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
--
2.42.1
next prev parent reply other threads:[~2023-11-17 20:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
2023-11-17 20:43 ` Xi Ruoyao [this message]
2023-11-17 20:43 ` [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
2023-11-20 23:15 ` Joseph Myers
2023-11-21 0:00 ` Xi Ruoyao
2023-11-21 3:09 ` Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution) Xi Ruoyao
2023-11-21 14:16 ` Jeff Law
2023-11-17 20:43 ` [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Xi Ruoyao
2023-11-18 8:13 ` [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support chenglulu
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