From: Xi Ruoyao <xry111@xry111.site>
To: gcc-patches@gcc.gnu.org
Cc: chenglulu <chenglulu@loongson.cn>,
i@xen0n.name, xuchenghua@loongson.cn,
Xi Ruoyao <xry111@xry111.site>
Subject: [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions
Date: Sat, 18 Nov 2023 04:43:20 +0800 [thread overview]
Message-ID: <20231117204323.453536-4-xry111@xry111.site> (raw)
In-Reply-To: <20231117204323.453536-1-xry111@xry111.site>
* config/loongarch/loongarch-def.h:
(loongarch_isa_base_features): Declare. Define it in ...
* config/loongarch/loongarch-cpu.cc
(loongarch_isa_base_features): ... here.
(fill_native_cpu_config): If we know the base ISA of the CPU
model from PRID, use it instead of la64 (v1.0). Check if all
expected features of this base ISA is available, emit a warning
if not.
* config/loongarch/loongarch-opts.cc (config_target_isa): Enable
the features implied by the base ISA if not -march=native.
---
gcc/config/loongarch/loongarch-cpu.cc | 62 ++++++++++++++++++--------
gcc/config/loongarch/loongarch-def.h | 5 +++
gcc/config/loongarch/loongarch-opts.cc | 3 ++
3 files changed, 52 insertions(+), 18 deletions(-)
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index f41e175257a..7acf1a9121d 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -32,6 +32,19 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
+/* loongarch_isa_base_features defined here instead of loongarch-def.c
+ because we need to use options.h. Pay attention on the order of elements
+ in the initializer becaue ISO C++ does not allow C99 designated
+ initializers! */
+
+#define ISA_BASE_LA64V110_FEATURES \
+ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA)
+
+int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
+ /* [ISA_BASE_LA64V100] = */ 0,
+ /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES,
+};
+
/* Native CPU detection with "cpucfg" */
static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
@@ -127,24 +140,22 @@ fill_native_cpu_config (struct loongarch_target *tgt)
With: base architecture (ARCH)
At: cpucfg_words[1][1:0] */
- switch (cpucfg_cache[1] & 0x3)
- {
- case 0x02:
- tmp = ISA_BASE_LA64V100;
- break;
-
- default:
- fatal_error (UNKNOWN_LOCATION,
- "unknown native base architecture %<0x%x%>, "
- "%qs failed", (unsigned int) (cpucfg_cache[1] & 0x3),
- "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE);
- }
-
- /* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
- warning (0, "base architecture %qs differs from PRID preset %qs",
- loongarch_isa_base_strings[tmp],
- loongarch_isa_base_strings[preset.base]);
+ if (native_cpu_type != CPU_NATIVE)
+ tmp = loongarch_cpu_default_isa[native_cpu_type].base;
+ else
+ switch (cpucfg_cache[1] & 0x3)
+ {
+ case 0x02:
+ tmp = ISA_BASE_LA64V100;
+ break;
+
+ default:
+ fatal_error (UNKNOWN_LOCATION,
+ "unknown native base architecture %<0x%x%>, "
+ "%qs failed",
+ (unsigned int) (cpucfg_cache[1] & 0x3),
+ "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE);
+ }
/* Use the native value anyways. */
preset.base = tmp;
@@ -227,6 +238,21 @@ fill_native_cpu_config (struct loongarch_target *tgt)
for (const auto &entry: cpucfg_map)
if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
preset.evolution |= entry.isa_evolution_bit;
+
+ if (native_cpu_type != CPU_NATIVE)
+ {
+ /* Check if the local CPU really supports the features of the base
+ ISA of probed native_cpu_type. If any feature is not detected,
+ either GCC or the hardware is buggy. */
+ auto base_isa_feature = loongarch_isa_base_features[preset.base];
+ if ((preset.evolution & base_isa_feature) != base_isa_feature)
+ warning (0,
+ "detected base architecture %qs, but some of its "
+ "features are not detected; the detected base "
+ "architecture may be unreliable, only detected "
+ "features will be enabled",
+ loongarch_isa_base_strings[preset.base]);
+ }
}
if (tune_native_p)
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 6123c8e0f19..af7bd635d6e 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -55,12 +55,17 @@ extern "C" {
/* enum isa_base */
extern const char* loongarch_isa_base_strings[];
+
/* LoongArch V1.00. */
#define ISA_BASE_LA64V100 0
/* LoongArch V1.10. */
#define ISA_BASE_LA64V110 1
#define N_ISA_BASE_TYPES 2
+/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is
+ we cannot use the C++ header options.h in loongarch-def.c. */
+extern int64_t loongarch_isa_base_features[];
+
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_NONE 0
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 67a59152a01..b5836f198c0 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -284,6 +284,9 @@ config_target_isa:
/* Get default ISA from "-march" or its default value. */
t.isa = loongarch_cpu_default_isa[t.cpu_arch];
+ if (t.cpu_arch != CPU_NATIVE)
+ t.isa.evolution |= loongarch_isa_base_features[t.isa.base];
+
/* Apply incremental changes. */
/* "-march=native" overrides the default FPU type. */
--
2.42.1
next prev parent reply other threads:[~2023-11-17 20:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 1/6] LoongArch: Fix internal error running "gcc -march=native" on LA664 Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
2023-11-20 23:15 ` Joseph Myers
2023-11-21 0:00 ` Xi Ruoyao
2023-11-21 3:09 ` Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution) Xi Ruoyao
2023-11-21 14:16 ` Jeff Law
2023-11-17 20:43 ` Xi Ruoyao [this message]
2023-11-17 20:43 ` [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Xi Ruoyao
2023-11-18 8:13 ` [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support chenglulu
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