From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 4050038582A6 for ; Fri, 17 Nov 2023 20:44:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4050038582A6 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4050038582A6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253853; cv=none; b=eYdYV/Au4hFhUIbNTKqO32Z8rT+cZsl1IUVDcXBGNSzfzT3Z6Y1S1/236PFw5JYE11R63OSlEteSeZtS5/liuqTObnZgRa39UPvjrNimMdMtuUP4717MaXTxCdPZ8lPBr5C5Bru0qYi7Wd2aeZl9JZTs+P4y7NGemkmabIbfxV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253853; c=relaxed/simple; bh=F2aRMQAay1CqGDhIsUzhWA7OGtFtRoh9nyJS/G1nveA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=itFU8czCU+w4FpNwUa3lIxEcqPanpCTDItL/nbyr4o2hf5Zvq3dBLlWX8qv0tEICA19n9eUnrMQQyzzgi9++vxbVy039R1L1q/OLKWC93rGT4BfB7TDl5N3DoFxlj5w2jt2Dmno7BVlHJxp5831svFcsCFG4joBG4hhWsLYaW1A= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700253851; bh=F2aRMQAay1CqGDhIsUzhWA7OGtFtRoh9nyJS/G1nveA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jkEs6ZVCePcCZVHHkEaTeoSj4ZCfTZv5hrDt1sX7ykA9787/UJVyHtKyNSAkN8J5F 0hFYREpzoj68rqmfhTI6gJp7QCPdzGkrGT4c3fd2lCQve8t/dPXAu+AJj9QOJzQfV/ cR/6fVRQ4EZID5d+yGRFHncbG9xIOm7PycNRpqqs= Received: from stargazer.. (unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id F132966B06; Fri, 17 Nov 2023 15:44:08 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Date: Sat, 18 Nov 2023 04:43:21 +0800 Message-ID: <20231117204323.453536-5-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits of a 64-bit GPR even if it's not sign-extended. gcc/ChangeLog: * config/loongarch/loongarch.md (DIV): New mode iterator. (3): Don't expand if TARGET_DIV32. (di3_fake): Disable if TARGET_DIV32. (*3): Allow SImode if TARGET_DIV32. (si3_extended): New insn if TARGET_DIV32. gcc/testsuite/ChangeLog: * gcc.target/loongarch/div-div32.c: New test. * gcc.target/loongarch/div-no-div32.c: New test. --- gcc/config/loongarch/loongarch.md | 31 ++++++++++++++++--- .../gcc.target/loongarch/div-div32.c | 31 +++++++++++++++++++ .../gcc.target/loongarch/div-no-div32.c | 11 +++++++ 3 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 22814a3679c..a97e5ee094a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -408,6 +408,10 @@ (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF]) ;; st.w. (define_mode_iterator ST_ANY [QHWD ANYF]) +;; A mode for anything legal as a input of a div or mod instruction. +(define_mode_iterator DIV [(DI "TARGET_64BIT") + (SI "!TARGET_64BIT || TARGET_DIV32")]) + ;; In GPR templates, a string like "mul." will expand to "mul.w" in the ;; 32-bit version and "mul.d" in the 64-bit version. (define_mode_attr d [(SI "w") (DI "d")]) @@ -914,7 +918,7 @@ (define_expand "3" (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode && TARGET_64BIT) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); @@ -934,9 +938,9 @@ (define_expand "3" }) (define_insn "*3" - [(set (match_operand:X 0 "register_operand" "=r,&r,&r") - (any_div:X (match_operand:X 1 "register_operand" "r,r,0") - (match_operand:X 2 "register_operand" "r,r,r")))] + [(set (match_operand:DIV 0 "register_operand" "=r,&r,&r") + (any_div:DIV (match_operand:DIV 1 "register_operand" "r,r,0") + (match_operand:DIV 2 "register_operand" "r,r,r")))] "" { return loongarch_output_division (".\t%0,%1,%2", operands); @@ -949,6 +953,23 @@ (define_insn "*3" (const_string "yes") (const_string "no")))]) +(define_insn "si3_extended" + [(set (match_operand:DI 0 "register_operand" "=r,&r,&r") + (sign_extend + (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0") + (match_operand:SI 2 "register_operand" "r,r,r"))))] + "TARGET_64BIT && TARGET_DIV32" +{ + return loongarch_output_division (".w\t%0,%1,%2", operands); +} + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set (attr "enabled") + (if_then_else + (match_test "!!which_alternative == loongarch_check_zero_div_p()") + (const_string "yes") + (const_string "no")))]) + (define_insn "di3_fake" [(set (match_operand:DI 0 "register_operand" "=r,&r,&r") (sign_extend:DI @@ -957,7 +978,7 @@ (define_insn "di3_fake" (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") (match_operand:DI 2 "register_operand" "r,r,r")) 0)] UNSPEC_FAKE_ANY_DIV)))] - "TARGET_64BIT" + "TARGET_64BIT && !TARGET_DIV32" { return loongarch_output_division (".w\t%0,%1,%2", operands); } diff --git a/gcc/testsuite/gcc.target/loongarch/div-div32.c b/gcc/testsuite/gcc.target/loongarch/div-div32.c new file mode 100644 index 00000000000..8b1f686eca2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-div32.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdiv32" } */ +/* { dg-final { scan-assembler "div\.w" } } */ +/* { dg-final { scan-assembler "div\.wu" } } */ +/* { dg-final { scan-assembler "mod\.w" } } */ +/* { dg-final { scan-assembler "mod\.wu" } } */ +/* { dg-final { scan-assembler-not "slli\.w.*,0" } } */ + +int +divw (long a, long b) +{ + return (int)a / (int)b; +} + +unsigned int +divwu (long a, long b) +{ + return (unsigned int)a / (unsigned int)b; +} + +int +modw (long a, long b) +{ + return (int)a % (int)b; +} + +unsigned int +modwu (long a, long b) +{ + return (unsigned int)a % (unsigned int)b; +} diff --git a/gcc/testsuite/gcc.target/loongarch/div-no-div32.c b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c new file mode 100644 index 00000000000..f0f697ba589 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */ +/* { dg-final { scan-assembler "div\.w" } } */ +/* { dg-final { scan-assembler "div\.wu" } } */ +/* { dg-final { scan-assembler "mod\.w" } } */ +/* { dg-final { scan-assembler "mod\.wu" } } */ + +/* -mno-div32 should be implied by -march=loongarch64. */ +/* { dg-final { scan-assembler-times "slli\.w\[^\n\]*0" 8 } } */ + +#include "div-div32.c" -- 2.42.1