From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id E888B385772E for ; Fri, 17 Nov 2023 20:44:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E888B385772E Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E888B385772E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253857; cv=none; b=Kl4Bz95nqbpOUsdgZWGSKMdgjSX0on7Au8s+j/WmBeGf90elLQYrWA2mSxa25KU9KhU6V3gS63VKU39mKds4Mg7NSrfPjgoZuMKkAwsw6zPKOlH20womqkh0oZoFzrbRz4hDsu9f/w89C4mJ2/GHWj3Va/+yY6eZbJUwd6jugGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253857; c=relaxed/simple; bh=0lj99FZkrpKBwSDWpTjwS0XdyNjjPkk3rdIq2/zoewU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=nk9tLM0E+ulcMiReFsV55g1av9qXwEQq+ypU+26XOl1WWcmrd+hMY6tiElPz27l1Tg0Ok58NHwF3uOczsHENeNFpw9Wfc1966CwW3Ljt+k77UmUTMv0QZJa+11jdXyDkDGaa2ErAyCebxDc4fhMbm672SxAuH+Toml9b6+fy9q0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700253855; bh=0lj99FZkrpKBwSDWpTjwS0XdyNjjPkk3rdIq2/zoewU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JnaHZv1NNPDlG2XAy6onSEzrlEDCPDJYhYoVkqcuUJSzZ1Ot3dkjLAnoMOjpRdJNV nxdBczUN924TwRmm+As9U6L+fklu9jINz6ESTyNG7RYLUw7lZZLrlBVLX27SDF3jL6 L71gtGnZ8XO+OKDKJAxotZ+iViAjwl0bopNmQxOg= Received: from stargazer.. (unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 4363F66B3B; Fri, 17 Nov 2023 15:44:11 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Date: Sat, 18 Nov 2023 04:43:22 +0800 Message-ID: <20231117204323.453536-6-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that two loads on the same address won't be reordered with each other". Thus we can omit the "load-load" barrier dbar 0x700. This is only a micro-optimization because dbar 0x700 is already treated as nop if the hardware supports LD_SEQ_SA. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand): Don't print dbar 0x700 if TARGET_LD_SEQ_SA. * config/loongarch/sync.md (atomic_load): Likewise. --- gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/sync.md | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index b4bb2b6eeb5..5d3282c5e93 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -6057,7 +6057,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter) if (loongarch_cas_failure_memorder_needs_acquire ( memmodel_from_int (INTVAL (op)))) fputs ("dbar\t0b10100", file); - else + else if (!TARGET_LD_SEQ_SA) fputs ("dbar\t0x700", file); break; diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 67848d72b87..ce3ce89a61d 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -119,13 +119,14 @@ (define_insn "atomic_load" case MEMMODEL_SEQ_CST: return "dbar\t0x11\\n\\t" "ld.\t%0,%1\\n\\t" - "dbar\t0x14\\n\\t"; + "dbar\t0x14"; case MEMMODEL_ACQUIRE: return "ld.\t%0,%1\\n\\t" - "dbar\t0x14\\n\\t"; + "dbar\t0x14"; case MEMMODEL_RELAXED: - return "ld.\t%0,%1\\n\\t" - "dbar\t0x700\\n\\t"; + return TARGET_LD_SEQ_SA ? "ld.\t%0,%1\\n\\t" + : "ld.\t%0,%1\\n\\t" + "dbar\t0x700"; default: /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST, -- 2.42.1