From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 2EFB83857BB8 for ; Fri, 17 Nov 2023 20:44:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2EFB83857BB8 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2EFB83857BB8 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253861; cv=none; b=NT2eJO6FTmdUwCo9biqmTK2G4ibtyGvTLBhdTHNMzZfmldn8pEcwg0hXyIWoA27DqttDwedsa3owga2IfZttsMTMbPWL2htDr2qgrBRg/DwFtSJDM7NbmMPHVkvQCYK6u4eM4wiIwr3IRB+llXD1Rkdc1Fi4AcO7Y6KMGR3Bdpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700253861; c=relaxed/simple; bh=WoFtCuyCyIGriKy5l7BwL9lQVeq0Y1WLUB+2+jXyyK0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=nifitUrU/4htDRWtfBth5swocX6Gu4sTFrZjCs4lYEXWK7ZjYatqF9v0lrP+QODm6l+9L2k+3ZP99nICpjHARF/frRkv2RgxZQds0S62CklajwvgAYwgLjJmlCzIhTs25ggh1GeynAlBg/LQItoOFYMq2putTGQTwAjGXAs/Acw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700253858; bh=WoFtCuyCyIGriKy5l7BwL9lQVeq0Y1WLUB+2+jXyyK0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UWat/N4Q+QJ+n454L+swevvsU4S+CtTa13R+AnhSZlAqaKNZ/uKGmXDW8A6L0YkQo OwT/D5KEOH9gZsxeuUnWbd4U9R7Jfsc1DrRVudwuc/K5XffAdUcwgLlgRUEnahkn/w 968321m1CG4dWZ4r7o6SKF2BpsdbzPCHdYV6D/dQ= Received: from stargazer.. (unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 1999E66B06; Fri, 17 Nov 2023 15:44:15 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Date: Sat, 18 Nov 2023 04:43:23 +0800 Message-ID: <20231117204323.453536-7-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas): Add. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-cpucfg-map.h: Regenerate. * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH and OPTION_MASK_ISA_LAMCAS. * config/loongarch/sync.md (atomic_add): Use TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty lines from assembly output. (atomic_exchange_short): Likewise. (atomic_exchange): Likewise. (atomic_fetch_add_short): Likewise. (atomic_fetch_add): Likewise. (atomic_cas_value_strong_amcas): Use TARGET_LAMCAS instead of ISA_BASE_IS_LA64V110. (atomic_compare_and_swap): Likewise. (atomic_compare_and_swap): Likewise. (atomic_compare_and_swap): Likewise. * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status if -mlam-bh and -mlamcas if -fverbose-asm. --- gcc/config/loongarch/genopts/isa-evolution.in | 2 ++ gcc/config/loongarch/loongarch-cpu.cc | 3 ++- gcc/config/loongarch/loongarch-cpucfg-map.h | 2 ++ gcc/config/loongarch/loongarch-str.h | 2 ++ gcc/config/loongarch/loongarch.cc | 2 ++ gcc/config/loongarch/loongarch.opt | 8 ++++++++ gcc/config/loongarch/sync.md | 18 +++++++++--------- 7 files changed, 27 insertions(+), 10 deletions(-) diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in index e58f0d6a1a1..a6bc3f87f20 100644 --- a/gcc/config/loongarch/genopts/isa-evolution.in +++ b/gcc/config/loongarch/genopts/isa-evolution.in @@ -1,2 +1,4 @@ 2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. +2 27 lam-bh Support am{swap/add}[_db].{b/h} instructions. +2 28 lamcas Support amcas[_db].{b/h/w/d} instructions. 3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index 7acf1a9121d..622df47916f 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -38,7 +38,8 @@ along with GCC; see the file COPYING3. If not see initializers! */ #define ISA_BASE_LA64V110_FEATURES \ - (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA) + (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \ + | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS) int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { /* [ISA_BASE_LA64V100] = */ 0, diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h index 0c078c39786..02ff1671255 100644 --- a/gcc/config/loongarch/loongarch-cpucfg-map.h +++ b/gcc/config/loongarch/loongarch-cpucfg-map.h @@ -30,6 +30,8 @@ static constexpr struct { HOST_WIDE_INT isa_evolution_bit; } cpucfg_map[] = { { 2, 1u << 26, OPTION_MASK_ISA_DIV32 }, + { 2, 1u << 27, OPTION_MASK_ISA_LAM_BH }, + { 2, 1u << 28, OPTION_MASK_ISA_LAMCAS }, { 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA }, }; diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 889962e9ab0..0384493765c 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -70,6 +70,8 @@ along with GCC; see the file COPYING3. If not see #define STR_EXPLICIT_RELOCS_ALWAYS "always" #define OPTSTR_DIV32 "div32" +#define OPTSTR_LAM_BH "lam-bh" +#define OPTSTR_LAMCAS "lamcas" #define OPTSTR_LD_SEQ_SA "ld-seq-sa" #endif /* LOONGARCH_STR_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 5d3282c5e93..46a898b79b7 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -11451,6 +11451,8 @@ loongarch_asm_code_end (void) fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START, loongarch_isa_base_strings [la_target.isa.base]); DUMP_FEATURE (TARGET_DIV32); + DUMP_FEATURE (TARGET_LAM_BH); + DUMP_FEATURE (TARGET_LAMCAS); DUMP_FEATURE (TARGET_LD_SEQ_SA); } diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index a39eddc108b..4d36e3ec4de 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -267,6 +267,14 @@ mdiv32 Target Mask(ISA_DIV32) Var(isa_evolution) Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. +mlam-bh +Target Mask(ISA_LAM_BH) Var(isa_evolution) +Support am{swap/add}[_db].{b/h} instructions. + +mlamcas +Target Mask(ISA_LAMCAS) Var(isa_evolution) +Support amcas[_db].{b/h/w/d} instructions. + mld-seq-sa Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution) Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index ce3ce89a61d..229fc50360a 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -124,7 +124,7 @@ (define_insn "atomic_load" return "ld.\t%0,%1\\n\\t" "dbar\t0x14"; case MEMMODEL_RELAXED: - return TARGET_LD_SEQ_SA ? "ld.\t%0,%1\\n\\t" + return TARGET_LD_SEQ_SA ? "ld.\t%0,%1" : "ld.\t%0,%1\\n\\t" "dbar\t0x700"; @@ -193,7 +193,7 @@ (define_insn "atomic_add" (match_operand:SHORT 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amadd%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 4))]) @@ -230,7 +230,7 @@ (define_insn "atomic_exchange_short" UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:SHORT 2 "register_operand" "r"))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amswap%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -266,7 +266,7 @@ (define_insn "atomic_cas_value_strong_amcas" (match_operand:QHWD 3 "reg_or_0_operand" "rJ") (match_operand:SI 4 "const_int_operand")] ;; mod_s UNSPEC_COMPARE_AND_SWAP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAMCAS" "ori\t%0,%z2,0\n\tamcas%A4.\t%0,%z3,%1" [(set (attr "length") (const_int 8))]) @@ -296,7 +296,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -422,7 +422,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -642,7 +642,7 @@ (define_expand "atomic_exchange" (match_operand:SHORT 2 "register_operand"))] "" { - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAM_BH) emit_insn (gen_atomic_exchange_short (operands[0], operands[1], operands[2], operands[3])); else { @@ -663,7 +663,7 @@ (define_insn "atomic_fetch_add_short" (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amadd%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -678,7 +678,7 @@ (define_expand "atomic_fetch_add" UNSPEC_SYNC_OLD_OP))] "" { - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAM_BH) emit_insn (gen_atomic_fetch_add_short (operands[0], operands[1], operands[2], operands[3])); else -- 2.42.1