From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com,
christoph.muellner@vrull.eu,
"Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
Subject: [PATCH v2 1/9] RISC-V: minimal support for xtheadvector
Date: Sat, 18 Nov 2023 12:26:27 +0800 [thread overview]
Message-ID: <20231118042627.3598-1-cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com>
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
Contributors:
Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
Jin Ma <jinma@linux.alibaba.com>
Christoph Müllner <christoph.muellner@vrull.eu>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): : Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt: Add new mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 10 ++++++++++
gcc/config/riscv/riscv-c.cc | 4 ++++
gcc/config/riscv/riscv.opt | 2 ++
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++++
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++++
5 files changed, 40 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..914924171fd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"v", "zvl128b"},
{"v", "zve64d"},
+ {"xtheadvector", "zvl128b"},
+ {"xtheadvector", "zve64d"},
{"zve32f", "f"},
{"zve64f", "f"},
@@ -325,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, location_t loc)
error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
"extensions", arch);
+ if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector"))
+ error_at (loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+ "extensions", arch);
+
/* 'H' hypervisor extension requires base ISA with 32 registers. */
if (subset_list->lookup ("e") && subset_list->lookup ("h"))
error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
@@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+ {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V},
+ {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR},
{"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index b7f9ba204f7..184fff905b2 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -137,6 +137,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
riscv_ext_version_value (0, 11));
}
+ if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+ riscv_ext_version_value (0, 11));
+
/* Define architecture extension test macros. */
builtin_define_with_int_value ("__riscv_arch_test", 1);
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..72857aea352 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
Mask(XTHEADSYNC) Var(riscv_xthead_subext)
+Mask(XTHEADVECTOR) Var(riscv_xthead_subext)
+
TargetVariable
int riscv_xventana_subext
diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
new file mode 100644
index 00000000000..1c764241db6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_th_v_intrinsic != 11000
+#error "__riscv_th_v_intrinsic"
+#endif
+
+ return 0;
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
new file mode 100644
index 00000000000..d52921e1314
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadvector
+#error "Feature macro not defined"
+#endif
+
+int
+foo (int a)
+{
+ return a;
+}
\ No newline at end of file
--
2.17.1
next prev parent reply other threads:[~2023-11-18 4:26 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 4:22 [PATCH v2 0/9] RISC-V: Support XTheadVector extensions Jun Sha (Joshua)
2023-11-18 4:26 ` Jun Sha (Joshua) [this message]
2023-11-18 10:06 ` [PATCH v2 1/9] RISC-V: minimal support for xtheadvector Kito Cheng
2023-11-18 4:28 ` [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector Jun Sha (Joshua)
2023-11-18 10:13 ` Kito Cheng
2023-11-18 4:29 ` [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Jun Sha (Joshua)
2023-11-18 4:32 ` [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) Jun Sha (Joshua)
2023-11-18 4:34 ` [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Jun Sha (Joshua)
2023-11-18 4:35 ` [PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) Jun Sha (Joshua)
2023-11-18 4:37 ` [PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics Jun Sha (Joshua)
2023-11-18 4:39 ` [PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension Jun Sha (Joshua)
2023-12-20 12:20 ` [PATCH v3 0/6] RISC-V: Support " Jun Sha (Joshua)
2023-12-20 12:25 ` [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-20 18:14 ` Jeff Law
2023-12-27 2:46 ` 回复:[PATCH " joshua
2023-12-29 1:44 ` joshua
2023-12-20 12:27 ` [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns Jun Sha (Joshua)
2023-12-20 18:16 ` Jeff Law
2023-12-27 2:49 ` 回复:[PATCH " joshua
2023-12-28 15:50 ` Jeff Law
2023-12-20 12:30 ` [PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2023-12-20 12:32 ` [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-20 18:22 ` Jeff Law
2023-12-20 22:48 ` 钟居哲
2023-12-21 4:41 ` Jeff Law
2023-12-21 9:43 ` Kito Cheng
2023-12-25 6:25 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-25 6:37 ` juzhe.zhong
2023-12-25 7:08 ` 回复:[PATCH " joshua
2023-12-25 7:09 ` juzhe.zhong
2023-12-25 8:14 ` [PATCH " Jun Sha (Joshua)
2023-12-25 8:18 ` juzhe.zhong
2023-12-20 12:34 ` [PATCH v3 5/6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2023-12-20 14:00 ` 钟居哲
2023-12-20 14:24 ` 回复:[PATCH " joshua
2023-12-20 14:27 ` 钟居哲
2023-12-20 14:41 ` 回复:回复:[PATCH " joshua
2023-12-20 14:48 ` 回复:[PATCH " 钟居哲
2023-12-20 14:55 ` 钟居哲
2023-12-20 15:21 ` 回复:回复:[PATCH " joshua
2023-12-20 15:29 ` 回复:[PATCH " 钟居哲
2023-12-25 6:29 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:46 ` Jun Sha (Joshua)
2023-12-29 1:58 ` juzhe.zhong
2023-12-29 2:09 ` 回复:[PATCH " joshua
2023-12-29 2:11 ` Re:[PATCH " joshua
2023-12-29 2:14 ` 回复:[PATCH " juzhe.zhong
2023-12-29 2:17 ` Re:[PATCH " joshua
2023-12-29 2:22 ` juzhe.zhong
2023-12-29 2:25 ` Re:Re:[PATCH " joshua
2023-12-29 2:25 ` Re:[PATCH " juzhe.zhong
2023-12-29 2:30 ` joshua
2023-12-29 2:31 ` juzhe.zhong
2023-12-29 2:47 ` juzhe.zhong
2023-12-20 12:36 ` [PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2023-12-25 6:31 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:49 ` Jun Sha (Joshua)
2023-12-20 23:04 ` [PATCH v3 0/6] RISC-V: Support XTheadVector extension 钟居哲
2023-12-22 3:33 ` 回复:[PATCH " joshua
2023-12-22 8:07 ` juzhe.zhong
2023-12-22 10:29 ` 回复:回复:[PATCH " joshua
2023-12-22 10:31 ` 回复:[PATCH " juzhe.zhong
2023-12-23 3:37 ` 回复:回复:[PATCH " joshua
2023-12-23 22:52 ` 回复:[PATCH " 钟居哲
2023-12-22 17:21 ` Jeff Law
2023-12-20 23:08 ` [PATCH " 钟居哲
2023-12-21 3:28 ` Jeff Law
2023-12-21 3:30 ` juzhe.zhong
2023-12-21 4:04 ` Jeff Law
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231118042627.3598-1-cooper.joshua@linux.alibaba.com \
--to=cooper.joshua@linux.alibaba.com \
--cc=andrew@sifive.com \
--cc=christoph.muellner@vrull.eu \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=jim.wilson.gcc@gmail.com \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).