From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com,
christoph.muellner@vrull.eu,
"Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
Subject: [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)
Date: Sat, 18 Nov 2023 12:32:27 +0800 [thread overview]
Message-ID: <20231118043227.3757-1-cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com>
For big changes in instruction generation, we can only duplicate
some typical tests in testsuite/gcc.target/riscv/rvv/base.
This patch is adding some tests for binary operations.
Contributors:
Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
Jin Ma <jinma@linux.alibaba.com>
Christoph Müllner <christoph.muellner@vrull.eu>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c: New test.
---
.../rvv/xtheadvector/binop_vx_constraint-11.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-12.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-13.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-14.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-15.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-16.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-17.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-18.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-19.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-20.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-21.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-22.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-23.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-24.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-25.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-26.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-27.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-28.c | 68 +++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-29.c | 73 +++++++++++++++++++
.../rvv/xtheadvector/binop_vx_constraint-30.c | 68 +++++++++++++++++
20 files changed, 1405 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c
new file mode 100644
index 00000000000..f9671318a67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c
new file mode 100644
index 00000000000..3e991339a22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c
new file mode 100644
index 00000000000..068e9c32511
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c
new file mode 100644
index 00000000000..26af4748453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, -16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, -16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, -16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c
new file mode 100644
index 00000000000..f19130108df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, 15, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c
new file mode 100644
index 00000000000..3134d1ebe5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4);
+ vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, 16, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c
new file mode 100644
index 00000000000..82e7c668e59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c
new file mode 100644
index 00000000000..57c548b25c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmul_vx_i32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c
new file mode 100644
index 00000000000..8406970e64e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c
new file mode 100644
index 00000000000..6b34dfa9c79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmax_vx_i32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c
new file mode 100644
index 00000000000..e73bc0f68bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c
new file mode 100644
index 00000000000..04f2d292bb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vmin_vx_i32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c
new file mode 100644
index 00000000000..6ce0d028347
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c
new file mode 100644
index 00000000000..0536eba14b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c
new file mode 100644
index 00000000000..291b0afdf85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c
new file mode 100644
index 00000000000..9c85da5b605
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c
new file mode 100644
index 00000000000..bea468b263a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c
new file mode 100644
index 00000000000..2640324cb4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4);
+ vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c
new file mode 100644
index 00000000000..66361ad567d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** ...
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c
new file mode 100644
index 00000000000..901e03bc181
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+** ...
+** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+** th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+ vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+ vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+ vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+ __riscv_vse32_v_u32m1 (out, v4, 4);
+}
--
2.17.1
next prev parent reply other threads:[~2023-11-18 4:32 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 4:22 [PATCH v2 0/9] RISC-V: Support XTheadVector extensions Jun Sha (Joshua)
2023-11-18 4:26 ` [PATCH v2 1/9] RISC-V: minimal support for xtheadvector Jun Sha (Joshua)
2023-11-18 10:06 ` Kito Cheng
2023-11-18 4:28 ` [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector Jun Sha (Joshua)
2023-11-18 10:13 ` Kito Cheng
2023-11-18 4:29 ` [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Jun Sha (Joshua)
2023-11-18 4:32 ` Jun Sha (Joshua) [this message]
2023-11-18 4:34 ` [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Jun Sha (Joshua)
2023-11-18 4:35 ` [PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) Jun Sha (Joshua)
2023-11-18 4:37 ` [PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics Jun Sha (Joshua)
2023-11-18 4:39 ` [PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension Jun Sha (Joshua)
2023-12-20 12:20 ` [PATCH v3 0/6] RISC-V: Support " Jun Sha (Joshua)
2023-12-20 12:25 ` [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-20 18:14 ` Jeff Law
2023-12-27 2:46 ` 回复：[PATCH " joshua
2023-12-29 1:44 ` joshua
2023-12-20 12:27 ` [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns Jun Sha (Joshua)
2023-12-20 18:16 ` Jeff Law
2023-12-27 2:49 ` 回复：[PATCH " joshua
2023-12-28 15:50 ` Jeff Law
2023-12-20 12:30 ` [PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2023-12-20 12:32 ` [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-20 18:22 ` Jeff Law
2023-12-20 22:48 ` 钟居哲
2023-12-21 4:41 ` Jeff Law
2023-12-21 9:43 ` Kito Cheng
2023-12-25 6:25 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-25 6:37 ` juzhe.zhong
2023-12-25 7:08 ` 回复：[PATCH " joshua
2023-12-25 7:09 ` juzhe.zhong
2023-12-25 8:14 ` [PATCH " Jun Sha (Joshua)
2023-12-25 8:18 ` juzhe.zhong
2023-12-20 12:34 ` [PATCH v3 5/6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2023-12-20 14:00 ` 钟居哲
2023-12-20 14:24 ` 回复：[PATCH " joshua
2023-12-20 14:27 ` 钟居哲
2023-12-20 14:41 ` 回复：回复：[PATCH " joshua
2023-12-20 14:48 ` 回复：[PATCH " 钟居哲
2023-12-20 14:55 ` 钟居哲
2023-12-20 15:21 ` 回复：回复：[PATCH " joshua
2023-12-20 15:29 ` 回复：[PATCH " 钟居哲
2023-12-25 6:29 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:46 ` Jun Sha (Joshua)
2023-12-29 1:58 ` juzhe.zhong
2023-12-29 2:09 ` 回复：[PATCH " joshua
2023-12-29 2:11 ` Re：[PATCH " joshua
2023-12-29 2:14 ` 回复：[PATCH " juzhe.zhong
2023-12-29 2:17 ` Re：[PATCH " joshua
2023-12-29 2:22 ` juzhe.zhong
2023-12-29 2:25 ` Re：Re：[PATCH " joshua
2023-12-29 2:25 ` Re：[PATCH " juzhe.zhong
2023-12-29 2:30 ` joshua
2023-12-29 2:31 ` juzhe.zhong
2023-12-29 2:47 ` juzhe.zhong
2023-12-20 12:36 ` [PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2023-12-25 6:31 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:49 ` Jun Sha (Joshua)
2023-12-20 23:04 ` [PATCH v3 0/6] RISC-V: Support XTheadVector extension 钟居哲
2023-12-22 3:33 ` 回复：[PATCH " joshua
2023-12-22 8:07 ` juzhe.zhong
2023-12-22 10:29 ` 回复：回复：[PATCH " joshua
2023-12-22 10:31 ` 回复：[PATCH " juzhe.zhong
2023-12-23 3:37 ` 回复：回复：[PATCH " joshua
2023-12-23 22:52 ` 回复：[PATCH " 钟居哲
2023-12-22 17:21 ` Jeff Law
2023-12-20 23:08 ` [PATCH " 钟居哲
2023-12-21 3:28 ` Jeff Law
2023-12-21 3:30 ` juzhe.zhong
2023-12-21 4:04 ` Jeff Law
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