From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-119.freemail.mail.aliyun.com (out30-119.freemail.mail.aliyun.com [115.124.30.119]) by sourceware.org (Postfix) with ESMTPS id EC00D3858D1E for ; Sat, 18 Nov 2023 04:32:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC00D3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EC00D3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.119 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700281970; cv=none; b=GAIgOmjR9GkCgT1Ulsd3O5SiAl/iDHCHRwKJkE+JM6Wrz/JD4Exu27ABYA9Yg6TmPFqyVG/YGjhbN1NlxYK+isSaQXLVtNN2+Bo036GWBf7lR5TkHJ73pGQ403M814iX7xOUek8e/IuhTG8fuj3TG6Xbdx69h4QWKulahVxHgm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700281970; c=relaxed/simple; bh=aR5kurZWY0S0/GReooXEfY6Z/x3tP/zcDPthNzbrcqY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=CVi6udGlLnmqyHB2mWF2lM2xD+rWlxdB7nMigHTOh0NMoOvUAs5GNMNkiqmvSW9V/uO2ba2enAAyn5Aq4M920ThBzm4iLXR3QDqhhH+RVLv1YmtFHP4ffJpLAbTTAy0CaQFCSDC4XhBfCVIaQ+ZsO0NtsCRw7YX6iJwZHTzRw7g= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R921e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=cooper.joshua@linux.alibaba.com;NM=1;PH=DS;RN=8;SR=0;TI=SMTPD_---0VwbPJOY_1700281957; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VwbPJOY_1700281957) by smtp.aliyun-inc.com; Sat, 18 Nov 2023 12:32:40 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" Subject: [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) Date: Sat, 18 Nov 2023 12:32:27 +0800 Message-Id: <20231118043227.3757-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> References: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.8 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c: New test. * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c: New test. --- .../rvv/xtheadvector/binop_vx_constraint-11.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-12.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-13.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-14.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-15.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-16.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-17.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-18.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-19.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-20.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-21.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-22.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-23.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-24.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-25.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-26.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-27.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-28.c | 68 +++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-29.c | 73 +++++++++++++++++++ .../rvv/xtheadvector/binop_vx_constraint-30.c | 68 +++++++++++++++++ 20 files changed, 1405 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c new file mode 100644 index 00000000000..f9671318a67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c new file mode 100644 index 00000000000..3e991339a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vand_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vand_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c new file mode 100644 index 00000000000..068e9c32511 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c new file mode 100644 index 00000000000..26af4748453 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c new file mode 100644 index 00000000000..f19130108df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** th.vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 15, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, 15, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c new file mode 100644 index 00000000000..3134d1ebe5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tu (v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_m (mask, v3, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vor_vx_i32m1 (v2, 16, 4); + vint32m1_t v4 = __riscv_vor_vx_i32m1_tumu (mask, v3, v2, 16, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c new file mode 100644 index 00000000000..82e7c668e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c new file mode 100644 index 00000000000..57c548b25c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmul_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmul_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c new file mode 100644 index 00000000000..8406970e64e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c new file mode 100644 index 00000000000..6b34dfa9c79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmax_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmax_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c new file mode 100644 index 00000000000..e73bc0f68bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c new file mode 100644 index 00000000000..04f2d292bb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vmin_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vmin_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c new file mode 100644 index 00000000000..6ce0d028347 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c new file mode 100644 index 00000000000..0536eba14b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vmaxu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vmaxu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c new file mode 100644 index 00000000000..291b0afdf85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c new file mode 100644 index 00000000000..9c85da5b605 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vminu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vminu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c new file mode 100644 index 00000000000..bea468b263a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 5, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c new file mode 100644 index 00000000000..2640324cb4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_m (mask, v3, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vdiv_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c new file mode 100644 index 00000000000..66361ad567d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, 5, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c new file mode 100644 index 00000000000..901e03bc181 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vse\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** ... +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vse.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4); + vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, x, 4); + __riscv_vse32_v_u32m1 (out, v4, 4); +} -- 2.17.1