From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 254663856DE6 for ; Sun, 19 Nov 2023 05:37:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 254663856DE6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 254663856DE6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::532 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372281; cv=none; b=X3o298ZKs/aU9KDjv+EM59ar+U/sZvqmMQNRtNYfwdp2PujGp4yiHZsp/H8/5nkvJ1z0C8X5iISgpgu6NlCP7jga3KvMhbAQ15A9BfTT3egwKKhzBxsaQZK5GCh1L3HNdEgrZj1JLOAW6paQBnXeKo2GPSraW/GHUi4AkL1q2g8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372281; c=relaxed/simple; bh=M9wfd6iMkH9cSAXAPIBPDrADCr+xc+9umVKHY/rF06I=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=wyvA5J00ph00PQ+GuH2bVdfPNjq1dpq6oaCVbfRQp3Yk4gFfSpm2Rx2LWjsTgN1E2yHQtd9Obgu1rTGevl31HyMqp5Hrc4Y6v8RmzxLCaupUi9NVMvnMZJsmq7OALmZtW7C+oFynQP535eiEVGDMSAsAhtnSN5hNLO+BkAfVhBM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-53e04b17132so4709358a12.0 for ; Sat, 18 Nov 2023 21:37:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1700372274; x=1700977074; darn=gcc.gnu.org; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=GmD8zERWYvjGz15uJ9wpZexX00zqLJgFeyzMRyR8dU4=; b=In7Fg5upyE4pzkxkhthcro5P5PCRftySUHKYCzzaYefTtgAkbHxNIKhPwHg+Yet/n5 mCWZrfeTtz+vEkyU0ubsnP/RsN3qr7EITENrnKGEU5K97EUFOfQa7Mw/ZR4BhzUGX1jY auxzq+Rd2pvp8Kn4SJAh5UZwRKAyABweDB5xM7bCgb5iHWbA90y5PabUZ2DTZcICx0IT Hsy7MoxOOyRmKMlCjJOHz8wBHWx7N53elGoqEHAYD461ho85vm/nE/kxqWRNUBeaplDe IFvwkNh8hcniAeLFlM77UubP6eDXD2FZXa8wnyzF3Wz4cab7bps6MSWVllVV2RMSZ8JZ xozA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700372274; x=1700977074; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=GmD8zERWYvjGz15uJ9wpZexX00zqLJgFeyzMRyR8dU4=; b=gbLxkC+AfOYjGVbPOMcjna90LZmUysRIWJo7L02F+1bAMztJDiU12Gz8N8sN7dbhKA 4qvQGgTwam3lQ/eSmBg/kHzXVN/JSwd5VrAh7TzV3eOdLD5dhLLpZLhyrXsinvTwQUvF hKtHsY6SY5JeLilyfZhfQVbFgHKZhKQCrsv8Iys0FM3eUelQ41mJHwvMK+tWMlSaNEiF xJwswuwO654CAh2RdomYwQnqgbHcjpEgUhH2mhhItzSP4alJhq8JFvTolH3WPQk1HLr5 mr04z38knGIYmqCeZE3yo2izb6HppERXaMouReB/kbNtS4gqpYIEo+Ke/oM/xGBtPHgK d5mA== X-Gm-Message-State: AOJu0Yxa7z1Ev0MdrWPXt0Sd26pUILtKDjsVEi6YKQLQVX15BddTEcn8 nbIyaMSXM7EV89JcmR5dfF3FNf/w4P3FoCt+6KPosQ== X-Google-Smtp-Source: AGHT+IFhO9Lr7SrSBwBB/5ybHgLKNl8meE3IhS1fhSlaMAI8P/86t0addxOqMpNNCutY4P7QkP0pJg== X-Received: by 2002:a05:6402:1116:b0:543:5281:2ad8 with SMTP id u22-20020a056402111600b0054352812ad8mr2627692edv.18.1700372273588; Sat, 18 Nov 2023 21:37:53 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id k5-20020a17090666c500b009e603786444sm2541838ejp.90.2023.11.18.21.37.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Nov 2023 21:37:53 -0800 (PST) Date: Sun, 19 Nov 2023 05:37:47 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_ASCII_DIVIDERS,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Message-ID: <20231119053747.5bqLuRwKUtYPOKNnU2inEyJpyVNCufBP-wZQMDujD8w@z> Verify, for short forward branch, T-Head, Ventana and Zicond targets and the ordered floating-point conditional-move operations that already work as expected, that if-conversion triggers via `noce_try_cmove' at the respective sufficiently high `-mbranch-cost=' settings that make branchless code sequences produced by if-conversion cheaper than their original branched equivalents, and that extraneous instructions such as SNEZ, etc. are not present in output. Cover all ordered floating-point relational operations to make sure no corner case escapes. gcc/testsuite/ * gcc.target/riscv/movdifge-sfb.c: New test. * gcc.target/riscv/movdifge-thead.c: New test. * gcc.target/riscv/movdifge-ventana.c: New test. * gcc.target/riscv/movdifge-zicond.c: New test. * gcc.target/riscv/movdifgt-sfb.c: New test. * gcc.target/riscv/movdifgt-thead.c: New test. * gcc.target/riscv/movdifgt-ventana.c: New test. * gcc.target/riscv/movdifgt-zicond.c: New test. * gcc.target/riscv/movdifle-sfb.c: New test. * gcc.target/riscv/movdifle-thead.c: New test. * gcc.target/riscv/movdifle-ventana.c: New test. * gcc.target/riscv/movdifle-zicond.c: New test. * gcc.target/riscv/movdiflt-sfb.c: New test. * gcc.target/riscv/movdiflt-thead.c: New test. * gcc.target/riscv/movdiflt-ventana.c: New test. * gcc.target/riscv/movdiflt-zicond.c: New test. * gcc.target/riscv/movdifne-sfb.c: New test. * gcc.target/riscv/movdifne-thead.c: New test. * gcc.target/riscv/movdifne-ventana.c: New test. * gcc.target/riscv/movdifne-zicond.c: New test. * gcc.target/riscv/movsifge-sfb.c: New test. * gcc.target/riscv/movsifge-thead.c: New test. * gcc.target/riscv/movsifge-ventana.c: New test. * gcc.target/riscv/movsifge-zicond.c: New test. * gcc.target/riscv/movsifgt-sfb.c: New test. * gcc.target/riscv/movsifgt-thead.c: New test. * gcc.target/riscv/movsifgt-ventana.c: New test. * gcc.target/riscv/movsifgt-zicond.c: New test. * gcc.target/riscv/movsifle-sfb.c: New test. * gcc.target/riscv/movsifle-thead.c: New test. * gcc.target/riscv/movsifle-ventana.c: New test. * gcc.target/riscv/movsifle-zicond.c: New test. * gcc.target/riscv/movsiflt-sfb.c: New test. * gcc.target/riscv/movsiflt-thead.c: New test. * gcc.target/riscv/movsiflt-ventana.c: New test. * gcc.target/riscv/movsiflt-zicond.c: New test. * gcc.target/riscv/movsifne-sfb.c: New test. * gcc.target/riscv/movsifne-thead.c: New test. * gcc.target/riscv/movsifne-ventana.c: New test. * gcc.target/riscv/movsifne-zicond.c: New test. --- gcc/testsuite/gcc.target/riscv/movdifge-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifge-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifge-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifge-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifgt-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifle-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifle-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifle-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifle-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdiflt-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifne-sfb.c | 27 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifne-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifne-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdifne-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifge-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifge-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifge-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifge-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifgt-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifle-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifle-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifle-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifle-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c | 26 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsiflt-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifne-sfb.c | 27 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifne-thead.c | 25 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifne-ventana.c | 28 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsifne-zicond.c | 28 ++++++++++++++++++++++ 40 files changed, 1072 insertions(+) gcc-riscv-branch-cost-test-movccf.diff Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect short forward branch assembly like: + + fge.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifge-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifge-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect short forward branch assembly like: + + fgt.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifgt-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect short forward branch assembly like: + + fle.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifle-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifle-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect short forward branch assembly like: + + flt.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiflt-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifne-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifne-sfb.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect short forward branch assembly like: + + feq.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a1,a0 +1: + mv a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifne-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifne-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + th.mvnez a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifne-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifne-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + vt.maskc a1,a1,a5 + vt.maskcn a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdifne-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdifne-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + czero.eqz a1,a1,a5 + czero.nez a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect short forward branch assembly like: + + fge.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifge-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifge-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + fge.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect short forward branch assembly like: + + fgt.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifgt-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + fgt.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect short forward branch assembly like: + + fle.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifle-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifle-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + fle.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-sfb.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect short forward branch assembly like: + + flt.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a0,a1 +1: + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + th.mveqz a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + vt.maskc a0,a0,a5 + vt.maskcn a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiflt-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + flt.d a5,fa0,fa1 + czero.eqz a0,a0,a5 + czero.nez a5,a1,a5 + or a0,a5,a0 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifne-sfb.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifne-sfb.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect short forward branch assembly like: + + feq.d a5,fa0,fa1 + bne a5,zero,1f # movcc + mv a1,a0 +1: + mv a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifne-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifne-thead.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + th.mvnez a0,a1,a5 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifne-ventana.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifne-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + vt.maskc a1,a1,a5 + vt.maskcn a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsifne-zicond.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsifne-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + feq.d a5,fa0,fa1 + czero.eqz a1,a1,a5 + czero.nez a0,a0,a5 + or a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */