From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 75ACA3858D33 for ; Sun, 19 Nov 2023 14:08:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 75ACA3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 75ACA3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700402894; cv=none; b=WNRgPdl9AuhXS9SR2Np714TP5KkBwyZIiij4LK0G5TdixlIqynyStbT2uppTees0R/p0gq7CQilbIjQxsP9KquPVc0oilpwPMPHPG8gIkaEJNh2/kR01cwckDy0bobpCOaKGnwGhgm9oAMoC9+MRcvRoDtXPwnD/I5U/AMLqxnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700402894; c=relaxed/simple; bh=RPDuMEdr68CXB4UtpMzDxMC7TLb+kq/oFUaDQFWQ+io=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NBgeiJAPVfZO/Vc2k0G5tSTe9k4OxRmRhM7FXPOLVc0mpvYmeCEDhiXkF2SeDCCxH4zykgDHZMiH2cOjpVcNnPHJJSyrKpY3rstytU0IZ1aYF+3hCw0nFkeEBGDmd9gt0TC4A4VVG8+j2Etlho41olkVWdkeDH2d1lcvFTLJVq8= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp73t1700402885tg6ckske Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 19 Nov 2023 22:08:04 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: znfcQSa1hKaypnhTkC7wfH0fG4N6C5gXq555jK8REYidwn/zoX+iwIJ1U3L3S 2FIeu93rDCXFBmy+6WSbUkl8kPCMCjEGjIdR/aLVyeH17x1EdDmfd3YyHfG3fFTXXmHSY1y zFA0az9In0OoDH1+F9PL5ScTRs5Hab/+9aF8brN2cxerwFvwCKBlwrW597Cseos7t2VNDm4 bQnHamDM9S/j4oVNOtzNiGEsrqsB0REXouwwR+ywSBVCjugp6g5t2xkF5U28wafWI9PrHsT /HUyUWJyfe0oG0ACoLKN/G8Wg8kMUixiUIB8Jd0rKsug9B5ih/GEX6RE1lnOP8jeFmuS2Gj bR2teYU2VHJV/3fN8Pvw71eh6ppF/4MU2uL72jZkD8nB0bFDlhAuJoiDyr8qeXXF3E4voKO FzxeUgnTnH8= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13158198000202640369 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed V2] RISC-V: Optimize constant AVL for LRA pattern Date: Sun, 19 Nov 2023 22:08:03 +0800 Message-Id: <20231119140803.4168318-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This optimization was discovered in the tuple move splitted bug fix patch. Before this patch: vsetivli zero,4,e16,mf2,ta,ma lhu a3,96(a5) vlseg8e16.v v1,(a5) lw a4,%lo(e)(a2) vsetvli a6,zero,e64,m2,ta,ma addi a0,a7,8 vse16.v v1,0(a7) vse16.v v2,0(a0) addi a0,a0,8 vse16.v v3,0(a0) addi a0,a0,8 vse16.v v4,0(a0) addi a0,a0,8 vse16.v v5,0(a0) addi a0,a0,8 vse16.v v6,0(a0) addi a0,a0,8 vse16.v v7,0(a0) addi a0,a0,8 vse16.v v8,0(a0) After this patch: vsetivli zero,4,e64,m2,ta,ma addi a0,a7,8 vlseg8e16.v v1,(a5) vse16.v v1,0(a7) vse16.v v2,0(a0) addi a0,a0,8 vse16.v v3,0(a0) addi a0,a0,8 vse16.v v4,0(a0) addi a0,a0,8 vse16.v v5,0(a0) addi a0,a0,8 vse16.v v6,0(a0) addi a0,a0,8 vse16.v v7,0(a0) addi a0,a0,8 vse16.v v8,0(a0) gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/post-ra-avl.c: New test. --- gcc/config/riscv/riscv-v.cc | 20 ++++++++++++++++--- .../riscv/rvv/autovec/post-ra-avl.c | 16 +++++++++++++++ 2 files changed, 33 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index f769c1474e0..594cc4dd145 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -374,10 +374,24 @@ void emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { gcc_assert (!can_create_pseudo_p ()); + machine_mode mode = GET_MODE (ops[0]); - insn_expander e (insn_flags, true); - e.set_vl (vl); - e.emit_insn ((enum insn_code) icode, ops); + if (imm_avl_p (mode)) + { + /* Even though VL is a real hardreg already allocated since + it is post-RA now, we still gain benefits that we emit + vsetivli zero, imm instead of vsetvli VL, zero which is + we can be more flexible in post-RA instruction scheduling. */ + insn_expander e (insn_flags, false); + e.set_vl (gen_int_mode (GET_MODE_NUNITS (mode), Pmode)); + e.emit_insn ((enum insn_code) icode, ops); + } + else + { + insn_expander e (insn_flags, true); + e.set_vl (vl); + e.emit_insn ((enum insn_code) icode, ops); + } } /* Emit an RVV insn with a predefined vector length. Contrary to diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c new file mode 100644 index 00000000000..f3d12bac7cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ + +int a, b, c, e; +short d[7][7] = {}; +int foo() { + short f; + c = 0; + for (; c <= 6; c++) { + e |= d[c][c] & 1; + b &= f & 3; + } + return a; +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero} 1 } } */ -- 2.36.3