From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 561D83858D37 for ; Sun, 19 Nov 2023 14:30:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 561D83858D37 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 561D83858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700404261; cv=none; b=roYIf79qbkeEUz3lGcXwcwFjMR7+XTTuPMypFp/Ipx3eiDTbZLnYNgV+3t8R+GikV3aM2rkxNPdBkGSGegDljlOyUl2aGbppCbKt/Urd7UHPrZy1uFA1IdPWd7JgVEM7BOYi+uSpHQdC3/OPln5l64VGLpQl/ianlBXtf0SrLvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700404261; c=relaxed/simple; bh=SzRAGfUgD+TpsuEvpbjb4OR3oHotc9+zOq7+mwS1a1M=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=x7Dplp4q+GZR41vPp24fskenJTSJETmoKI1G9MqVkyHCk2xYpgcA/rHG98t7B+XaDaTgH/Jx3wxu3TAZePj4Bv4zieAKSzzj9DMJv78ObdcWgIORoPbEIwQ7v3ad7p+88+NU9S3ewwHeSHcyRYB/9rA6j1oCUNJr8hMdifIvAjU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700404258; bh=SzRAGfUgD+TpsuEvpbjb4OR3oHotc9+zOq7+mwS1a1M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mM+AodfbdxIIxlIA+/D7PPykKiWey2GEnGHPWgCoaGBWPG2xTcRkeJnojps5SxJYj xUmUL/dd4p4BqyJ8YikEWn2axrUZlKwQrDJKbHQHIPprmv1Xw28ILdoP8eoppWwdNi HakSPO5TvuxiP9YrbuAfobYGg6IWIg/WWBiBB1tA= Received: from stargazer.. (unknown [124.115.222.147]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 815F366C08; Sun, 19 Nov 2023 09:30:57 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 2/3] LoongArch: Use standard pattern name and RTX code for LSX/LASX muh instructions Date: Sun, 19 Nov 2023 22:30:36 +0800 Message-ID: <20231119143037.16443-3-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231119143037.16443-1-xry111@xry111.site> References: <20231119143037.16443-1-xry111@xry111.site> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,RCVD_IN_ABUSEAT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Removes unnecessary UNSPECs and make the muh instructions useful with GNU vectors or auto vectorization. gcc/ChangeLog: * config/loongarch/simd.md (muh): New code attribute mapping any_extend to smul_highpart or umul_highpart. (mul3_highpart): New define_insn. * config/loongarch/lsx.md (UNSPEC_LSX_VMUH_S): Remove. (UNSPEC_LSX_VMUH_U): Remove. (lsx_vmuh_s_): Remove. (lsx_vmuh_u_): Remove. * config/loongarch/lasx.md (UNSPEC_LASX_XVMUH_S): Remove. (UNSPEC_LASX_XVMUH_U): Remove. (lasx_xvmuh_s_): Remove. (lasx_xvmuh_u_): Remove. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vmuh_b): Redefine to standard pattern name. (CODE_FOR_lsx_vmuh_h): Likewise. (CODE_FOR_lsx_vmuh_w): Likewise. (CODE_FOR_lsx_vmuh_d): Likewise. (CODE_FOR_lsx_vmuh_bu): Likewise. (CODE_FOR_lsx_vmuh_hu): Likewise. (CODE_FOR_lsx_vmuh_wu): Likewise. (CODE_FOR_lsx_vmuh_du): Likewise. (CODE_FOR_lasx_xvmuh_b): Likewise. (CODE_FOR_lasx_xvmuh_h): Likewise. (CODE_FOR_lasx_xvmuh_w): Likewise. (CODE_FOR_lasx_xvmuh_d): Likewise. (CODE_FOR_lasx_xvmuh_bu): Likewise. (CODE_FOR_lasx_xvmuh_hu): Likewise. (CODE_FOR_lasx_xvmuh_wu): Likewise. (CODE_FOR_lasx_xvmuh_du): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-muh.c: New test. --- gcc/config/loongarch/lasx.md | 22 ------------ gcc/config/loongarch/loongarch-builtins.cc | 32 ++++++++--------- gcc/config/loongarch/lsx.md | 22 ------------ gcc/config/loongarch/simd.md | 16 +++++++++ gcc/testsuite/gcc.target/loongarch/vect-muh.c | 36 +++++++++++++++++++ 5 files changed, 68 insertions(+), 60 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-muh.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index a5eb878a612..51574bf043d 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -68,8 +68,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_BRANCH UNSPEC_LASX_BRANCH_V - UNSPEC_LASX_XVMUH_S - UNSPEC_LASX_XVMUH_U UNSPEC_LASX_MXVEXTW_U UNSPEC_LASX_XVSLLWIL_S UNSPEC_LASX_XVSLLWIL_U @@ -2835,26 +2833,6 @@ (define_insn "neg2" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) -(define_insn "lasx_xvmuh_s_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVMUH_S))] - "ISA_HAS_LASX" - "xvmuh.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - -(define_insn "lasx_xvmuh_u_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVMUH_U))] - "ISA_HAS_LASX" - "xvmuh.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lasx_xvsllwil_s__" [(set (match_operand: 0 "register_operand" "=f") (unspec: [(match_operand:ILASX_WHB 1 "register_operand" "f") diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index cbd833aa283..a6fcc1c731e 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -319,6 +319,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vmod_hu CODE_FOR_umodv8hi3 #define CODE_FOR_lsx_vmod_wu CODE_FOR_umodv4si3 #define CODE_FOR_lsx_vmod_du CODE_FOR_umodv2di3 +#define CODE_FOR_lsx_vmuh_b CODE_FOR_smulv16qi3_highpart +#define CODE_FOR_lsx_vmuh_h CODE_FOR_smulv8hi3_highpart +#define CODE_FOR_lsx_vmuh_w CODE_FOR_smulv4si3_highpart +#define CODE_FOR_lsx_vmuh_d CODE_FOR_smulv2di3_highpart +#define CODE_FOR_lsx_vmuh_bu CODE_FOR_umulv16qi3_highpart +#define CODE_FOR_lsx_vmuh_hu CODE_FOR_umulv8hi3_highpart +#define CODE_FOR_lsx_vmuh_wu CODE_FOR_umulv4si3_highpart +#define CODE_FOR_lsx_vmuh_du CODE_FOR_umulv2di3_highpart #define CODE_FOR_lsx_vmul_b CODE_FOR_mulv16qi3 #define CODE_FOR_lsx_vmul_h CODE_FOR_mulv8hi3 #define CODE_FOR_lsx_vmul_w CODE_FOR_mulv4si3 @@ -439,14 +447,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vfnmsub_s CODE_FOR_vfnmsubv4sf4_nmsub4 #define CODE_FOR_lsx_vfnmsub_d CODE_FOR_vfnmsubv2df4_nmsub4 -#define CODE_FOR_lsx_vmuh_b CODE_FOR_lsx_vmuh_s_b -#define CODE_FOR_lsx_vmuh_h CODE_FOR_lsx_vmuh_s_h -#define CODE_FOR_lsx_vmuh_w CODE_FOR_lsx_vmuh_s_w -#define CODE_FOR_lsx_vmuh_d CODE_FOR_lsx_vmuh_s_d -#define CODE_FOR_lsx_vmuh_bu CODE_FOR_lsx_vmuh_u_bu -#define CODE_FOR_lsx_vmuh_hu CODE_FOR_lsx_vmuh_u_hu -#define CODE_FOR_lsx_vmuh_wu CODE_FOR_lsx_vmuh_u_wu -#define CODE_FOR_lsx_vmuh_du CODE_FOR_lsx_vmuh_u_du #define CODE_FOR_lsx_vsllwil_h_b CODE_FOR_lsx_vsllwil_s_h_b #define CODE_FOR_lsx_vsllwil_w_h CODE_FOR_lsx_vsllwil_s_w_h #define CODE_FOR_lsx_vsllwil_d_w CODE_FOR_lsx_vsllwil_s_d_w @@ -588,6 +588,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvmul_h CODE_FOR_mulv16hi3 #define CODE_FOR_lasx_xvmul_w CODE_FOR_mulv8si3 #define CODE_FOR_lasx_xvmul_d CODE_FOR_mulv4di3 +#define CODE_FOR_lasx_xvmuh_b CODE_FOR_smulv32qi3_highpart +#define CODE_FOR_lasx_xvmuh_h CODE_FOR_smulv16hi3_highpart +#define CODE_FOR_lasx_xvmuh_w CODE_FOR_smulv8si3_highpart +#define CODE_FOR_lasx_xvmuh_d CODE_FOR_smulv4di3_highpart +#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_umulv32qi3_highpart +#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_umulv16hi3_highpart +#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_umulv8si3_highpart +#define CODE_FOR_lasx_xvmuh_du CODE_FOR_umulv4di3_highpart #define CODE_FOR_lasx_xvclz_b CODE_FOR_clzv32qi2 #define CODE_FOR_lasx_xvclz_h CODE_FOR_clzv16hi2 #define CODE_FOR_lasx_xvclz_w CODE_FOR_clzv8si2 @@ -697,14 +705,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvavgr_hu CODE_FOR_lasx_xvavgr_u_hu #define CODE_FOR_lasx_xvavgr_wu CODE_FOR_lasx_xvavgr_u_wu #define CODE_FOR_lasx_xvavgr_du CODE_FOR_lasx_xvavgr_u_du -#define CODE_FOR_lasx_xvmuh_b CODE_FOR_lasx_xvmuh_s_b -#define CODE_FOR_lasx_xvmuh_h CODE_FOR_lasx_xvmuh_s_h -#define CODE_FOR_lasx_xvmuh_w CODE_FOR_lasx_xvmuh_s_w -#define CODE_FOR_lasx_xvmuh_d CODE_FOR_lasx_xvmuh_s_d -#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_lasx_xvmuh_u_bu -#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_lasx_xvmuh_u_hu -#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_lasx_xvmuh_u_wu -#define CODE_FOR_lasx_xvmuh_du CODE_FOR_lasx_xvmuh_u_du #define CODE_FOR_lasx_xvssran_b_h CODE_FOR_lasx_xvssran_s_b_h #define CODE_FOR_lasx_xvssran_h_w CODE_FOR_lasx_xvssran_s_h_w #define CODE_FOR_lasx_xvssran_w_d CODE_FOR_lasx_xvssran_s_w_d diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index af5b1bf89d7..13b313a7477 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -64,8 +64,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VSRLR UNSPEC_LSX_VSRLRI UNSPEC_LSX_VSHUF - UNSPEC_LSX_VMUH_S - UNSPEC_LSX_VMUH_U UNSPEC_LSX_VEXTW_S UNSPEC_LSX_VEXTW_U UNSPEC_LSX_VSLLWIL_S @@ -2515,26 +2513,6 @@ (define_insn "vneg2" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) -(define_insn "lsx_vmuh_s_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VMUH_S))] - "ISA_HAS_LSX" - "vmuh.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - -(define_insn "lsx_vmuh_u_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VMUH_U))] - "ISA_HAS_LSX" - "vmuh.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lsx_vextw_s_d" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index e8fbcfb2151..2e13978eb7b 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -186,6 +186,22 @@ (define_expand "fix_trunk2" UNSPEC_SIMD_FRINTRZ)))] "") +;; vmuh.{b/h/w/d} + +(define_code_attr muh + [(sign_extend "smul_highpart") + (zero_extend "umul_highpart")]) + +(define_insn "mul3_highpart" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:IVEC 2 "register_operand" "f"))) + (any_extend (const_int 0))] + "" + "vmuh.\t%0,%1,%2" + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vect-muh.c b/gcc/testsuite/gcc.target/loongarch/vect-muh.c new file mode 100644 index 00000000000..a788840b23c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-muh.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mlasx -O3" } */ +/* { dg-final { scan-assembler "\tvmuh\.w\t" } } */ +/* { dg-final { scan-assembler "\tvmuh\.wu\t" } } */ +/* { dg-final { scan-assembler "\txvmuh\.w\t" } } */ +/* { dg-final { scan-assembler "\txvmuh\.wu\t" } } */ + +int a[8], b[8], c[8]; + +void +test1 (void) +{ + for (int i = 0; i < 4; i++) + c[i] = ((long)a[i] * (long)b[i]) >> 32; +} + +void +test2 (void) +{ + for (int i = 0; i < 4; i++) + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; +} + +void +test3 (void) +{ + for (int i = 0; i < 8; i++) + c[i] = ((long)a[i] * (long)b[i]) >> 32; +} + +void +test4 (void) +{ + for (int i = 0; i < 8; i++) + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; +} -- 2.42.1