From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id E516C3858D38 for ; Sun, 19 Nov 2023 14:31:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E516C3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E516C3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700404262; cv=none; b=sC7+IC8PnBp1RoPw++WuGlA0Bo6XCmyZQ+AG+QK1d7Ah3fSqM/jvp2parGAzTyUjqlLOskFjyQYCCMGwaNTfdpwS05ZOU5SejNL84y4eNYQ3mHYIQwAArr1NIHphIMAwVCHsIzfd+TPPiMzAs9jULd0FVsp70nLnkia+wpmuSJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700404262; c=relaxed/simple; bh=IxbYVtvL5Qr3oCu9nqqLBt1fMqMkcQyScWq50xic+Dg=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=n09LkrvAE+Ol8w7MPTkeU1o5MCut1nvbcRG0xNIHRNd20E3kXTPfAH3jW1l4DLTkspzB3pS3YuFqeFrXz4rdIh15Gsb/CSfU4aOssPMC9+H69LgEMG+AAHnt+ZzpWkHbVHdgGLYC9Gfqa4IS1IE5rTR+kvoCrgtVJ+6Ad59Sf/A= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1700404260; bh=IxbYVtvL5Qr3oCu9nqqLBt1fMqMkcQyScWq50xic+Dg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W3timzYxFkOq75fRV6zeY1WqFX3Nq0EGu+zxLyrJG7hGyyt/7Fy2OL1QfP7XURUll HJtJABOxOjJEcynvzztJFtOxP49SlkxgfdTpoSm46b+Ny0Az90xh9YgWouZac6XYqK zLZ25jOc/O1TFzp9zYNB5j7+lVi6s380K41IjJ/U= Received: from stargazer.. (unknown [124.115.222.147]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 1359166C09; Sun, 19 Nov 2023 09:30:58 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 3/3] LoongArch: Use standard pattern name and RTX code for LSX/LASX rotate shift Date: Sun, 19 Nov 2023 22:30:37 +0800 Message-ID: <20231119143037.16443-4-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231119143037.16443-1-xry111@xry111.site> References: <20231119143037.16443-1-xry111@xry111.site> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,RCVD_IN_ABUSEAT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Remove unnecessary UNSPECs and make the [x]vrotr[i] instructions useful with GNU vectors and auto vectorization. gcc/ChangeLog: * config/loongarch/lsx.md (bitimm): Move to ... (UNSPEC_LSX_VROTR): Remove. (lsx_vrotr_): Remove. (lsx_vrotri_): Remove. * config/loongarch/lasx.md (UNSPEC_LASX_XVROTR): Remove. (lsx_vrotr_): Remove. (lsx_vrotri_): Remove. * config/loongarch/simd.md (bitimm): ... here. Expand it to cover LASX modes. (vrotr3): New define_insn. (vrotri3): New define_insn. * config/loongarch/loongarch-builtins.cc: (CODE_FOR_lsx_vrotr_b): Use standard pattern name. (CODE_FOR_lsx_vrotr_h): Likewise. (CODE_FOR_lsx_vrotr_w): Likewise. (CODE_FOR_lsx_vrotr_d): Likewise. (CODE_FOR_lasx_xvrotr_b): Likewise. (CODE_FOR_lasx_xvrotr_h): Likewise. (CODE_FOR_lasx_xvrotr_w): Likewise. (CODE_FOR_lasx_xvrotr_d): Likewise. (CODE_FOR_lsx_vrotri_b): Define to standard pattern name. (CODE_FOR_lsx_vrotri_h): Likewise. (CODE_FOR_lsx_vrotri_w): Likewise. (CODE_FOR_lsx_vrotri_d): Likewise. (CODE_FOR_lasx_xvrotri_b): Likewise. (CODE_FOR_lasx_xvrotri_h): Likewise. (CODE_FOR_lasx_xvrotri_w): Likewise. (CODE_FOR_lasx_xvrotri_d): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-rotr.c: New test. --- gcc/config/loongarch/lasx.md | 22 ------------ gcc/config/loongarch/loongarch-builtins.cc | 16 +++++++++ gcc/config/loongarch/lsx.md | 28 --------------- gcc/config/loongarch/simd.md | 29 +++++++++++++++ .../gcc.target/loongarch/vect-rotr.c | 36 +++++++++++++++++++ 5 files changed, 81 insertions(+), 50 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-rotr.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 51574bf043d..3e135387173 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -138,7 +138,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVHSUBW_Q_D UNSPEC_LASX_XVHADDW_QU_DU UNSPEC_LASX_XVHSUBW_QU_DU - UNSPEC_LASX_XVROTR UNSPEC_LASX_XVADD_Q UNSPEC_LASX_XVSUB_Q UNSPEC_LASX_XVREPLVE @@ -4244,18 +4243,6 @@ (define_insn "lasx_xvhsubw_qu_du" [(set_attr "type" "simd_int_arith") (set_attr "mode" "V4DI")]) -;;XVROTR.B XVROTR.H XVROTR.W XVROTR.D -;;TODO-478 -(define_insn "lasx_xvrotr_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVROTR))] - "ISA_HAS_LASX" - "xvrotr.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - ;;XVADD.Q ;;TODO2 (define_insn "lasx_xvadd_q" @@ -4438,15 +4425,6 @@ (define_insn "lasx_xvexth_qu_du" [(set_attr "type" "simd_fcvt") (set_attr "mode" "V4DI")]) -(define_insn "lasx_xvrotri_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (rotatert:ILASX (match_operand:ILASX 1 "register_operand" "f") - (match_operand 2 "const__operand" "")))] - "ISA_HAS_LASX" - "xvrotri.\t%u0,%u1,%2" - [(set_attr "type" "simd_shf") - (set_attr "mode" "")]) - (define_insn "lasx_xvextl_q_d" [(set (match_operand:V4DI 0 "register_operand" "=f") (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index a6fcc1c731e..5d037ab7f10 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -369,6 +369,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vsrli_h CODE_FOR_vlshrv8hi3 #define CODE_FOR_lsx_vsrli_w CODE_FOR_vlshrv4si3 #define CODE_FOR_lsx_vsrli_d CODE_FOR_vlshrv2di3 +#define CODE_FOR_lsx_vrotr_b CODE_FOR_vrotrv16qi3 +#define CODE_FOR_lsx_vrotr_h CODE_FOR_vrotrv8hi3 +#define CODE_FOR_lsx_vrotr_w CODE_FOR_vrotrv4si3 +#define CODE_FOR_lsx_vrotr_d CODE_FOR_vrotrv2di3 +#define CODE_FOR_lsx_vrotri_b CODE_FOR_rotrv16qi3 +#define CODE_FOR_lsx_vrotri_h CODE_FOR_rotrv8hi3 +#define CODE_FOR_lsx_vrotri_w CODE_FOR_rotrv4si3 +#define CODE_FOR_lsx_vrotri_d CODE_FOR_rotrv2di3 #define CODE_FOR_lsx_vsub_b CODE_FOR_subv16qi3 #define CODE_FOR_lsx_vsub_h CODE_FOR_subv8hi3 #define CODE_FOR_lsx_vsub_w CODE_FOR_subv4si3 @@ -634,6 +642,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvsrli_h CODE_FOR_vlshrv16hi3 #define CODE_FOR_lasx_xvsrli_w CODE_FOR_vlshrv8si3 #define CODE_FOR_lasx_xvsrli_d CODE_FOR_vlshrv4di3 +#define CODE_FOR_lasx_xvrotr_b CODE_FOR_vrotrv32qi3 +#define CODE_FOR_lasx_xvrotr_h CODE_FOR_vrotrv16hi3 +#define CODE_FOR_lasx_xvrotr_w CODE_FOR_vrotrv8si3 +#define CODE_FOR_lasx_xvrotr_d CODE_FOR_vrotrv4di3 +#define CODE_FOR_lasx_xvrotri_b CODE_FOR_rotrv32qi3 +#define CODE_FOR_lasx_xvrotri_h CODE_FOR_rotrv16hi3 +#define CODE_FOR_lasx_xvrotri_w CODE_FOR_rotrv8si3 +#define CODE_FOR_lasx_xvrotri_d CODE_FOR_rotrv4di3 #define CODE_FOR_lasx_xvsub_b CODE_FOR_subv32qi3 #define CODE_FOR_lasx_xvsub_h CODE_FOR_subv16hi3 #define CODE_FOR_lasx_xvsub_w CODE_FOR_subv8si3 diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 13b313a7477..1446c44b431 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -141,7 +141,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VMADDWOD UNSPEC_LSX_VMADDWOD2 UNSPEC_LSX_VMADDWOD3 - UNSPEC_LSX_VROTR UNSPEC_LSX_VADD_Q UNSPEC_LSX_VSUB_Q UNSPEC_LSX_VEXTH_Q_D @@ -363,14 +362,6 @@ (define_mode_attr bitmask (V8HI "exp_8") (V16QI "exp_16")]) -;; This attribute is used to form an immediate operand constraint using -;; "const__operand". -(define_mode_attr bitimm - [(V16QI "uimm3") - (V8HI "uimm4") - (V4SI "uimm5") - (V2DI "uimm6")]) - (define_expand "vec_init" [(match_operand:LSX 0 "register_operand") (match_operand:LSX 1 "")] @@ -4161,16 +4152,6 @@ (define_insn "lsx_vmaddwod_q_du_d" [(set_attr "type" "simd_int_arith") (set_attr "mode" "V2DI")]) -(define_insn "lsx_vrotr_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VROTR))] - "ISA_HAS_LSX" - "vrotr.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lsx_vadd_q" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f") @@ -4264,15 +4245,6 @@ (define_insn "lsx_vexth_qu_du" [(set_attr "type" "simd_fcvt") (set_attr "mode" "V2DI")]) -(define_insn "lsx_vrotri_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (rotatert:ILSX (match_operand:ILSX 1 "register_operand" "f") - (match_operand 2 "const__operand" "")))] - "ISA_HAS_LSX" - "vrotri.\t%w0,%w1,%2" - [(set_attr "type" "simd_shf") - (set_attr "mode" "")]) - (define_insn "lsx_vextl_q_d" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 2e13978eb7b..4ba73da48d6 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -72,6 +72,13 @@ (define_mode_attr elmbits [(V2DI "64") (V4DI "64") (V8HI "16") (V16HI "16") (V16QI "8") (V32QI "8")]) +;; This attribute is used to form an immediate operand constraint using +;; "const__operand". +(define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") + (V8HI "uimm4") (V16HI "uimm4") + (V4SI "uimm5") (V8SI "uimm5") + (V2DI "uimm6") (V4DI "uimm6")]) + ;; ======================================================================= ;; For many LASX instructions, the only difference of it from the LSX ;; counterpart is the length of vector operands. Describe these LSX/LASX @@ -202,6 +209,28 @@ (define_insn "mul3_highpart" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) +;; vrotr.{b/h/w/d} + +(define_insn "vrotr3" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:IVEC 2 "register_operand" "f")))] + "" + "vrotr.\t%0,%1,%2" + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + +;; vrotri.{b/h/w/d} + +(define_insn "rotr3" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:SI 2 "const__operand")))] + "" + "vrotri.\t%0,%1,%2"; + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vect-rotr.c b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c new file mode 100644 index 00000000000..733c36334ce --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx" } */ +/* { dg-final { scan-assembler "\tvrotr\.w\t" } } */ +/* { dg-final { scan-assembler "\txvrotr\.w\t" } } */ +/* { dg-final { scan-assembler "\tvrotri\.w\t\[^\n\]*7\n" } } */ +/* { dg-final { scan-assembler "\txvrotri\.w\t\[^\n\]*7\n" } } */ + +unsigned int a[8], b[8]; + +void +test1 (void) +{ + for (int i = 0; i < 4; i++) + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); +} + +void +test2 (void) +{ + for (int i = 0; i < 8; i++) + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); +} + +void +test3 (void) +{ + for (int i = 0; i < 4; i++) + a[i] = a[i] >> 7 | a[i] << 25; +} + +void +test4 (void) +{ + for (int i = 0; i < 8; i++) + a[i] = a[i] >> 7 | a[i] << 25; +} -- 2.42.1