From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 295753858C39 for ; Tue, 28 Nov 2023 08:00:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 295753858C39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 295753858C39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701158445; cv=none; b=PB96443DOzx68T4iWJPXAaem5vn8/myaTSAJ5r+usUipckANTny13hbOmJMQncA9yfJJIWF1HBkDhKroAlIdJk35oHM+6jzDrPVZ1GLWUGv1DUXHMUFvhLe40t/nUDYBbvxXTOuAmCTj1KGF9P2QIMi4OkS2RCy9Yh7BrPhrMmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701158445; c=relaxed/simple; bh=/SGjb3NYzDyHUGekCkw2btl3c8yfnM6WzrRcLDDMP88=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=AfYNb9Q6fnXxZD6kIUtKTQerEfxFDBijZCAswBbdxAE0eDqpmT2czOmMSh2sapH1K2DbBi+k2lGjTZ7+wapQJtLjT8wtPKZ0y+o2pUuK/eW6VdhKSINFT+63m9/88I7wp9fIQM3K0DtnpV/tLiB4gXwdhUt2NcYM58LlqcXhPnc= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1701158435t0cf7vmc Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 28 Nov 2023 16:00:34 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: GD9JVPP0MSa+2BVe3byAEaG/KAkHVrKe2JVzMP7Zk8wwNX2JGrqvHix/jVOFc qRL49rWMiYFHZggYTLIPuy5mFVQSq7A0eXVl6Fg02sMR4VSjAR6zZOIOmj6fRo0hgKEejmU JJwpoUa/GJgKIMpDhgsKn8lBtVrnEVALtihPrkijldI6a3Djyl3yQhBIVO4KjbL7Hnp9/1z J6vNR8kdMZDAHe5Ns9SojbfyR7llWN/IAHChmdGd2/cFPM21mopLwyteqZ6qXoKaZTjX1aq FARDovEs6lht28uDNKx/EFYNQldCGQePH38lHuLRSI4+4Y27Mk/UVLt6QEWT0H2QSMLN8X4 NPBV/vO9+r2mxmG7EUziXL2yUd+cIxChBMWaq0efpqDv6YjpsrS2mvlSl8L5gfRn5rNkssJ DAI9fZmS2MQ= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11317671096964737742 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization Date: Tue, 28 Nov 2023 16:00:33 +0800 Message-Id: <20231128080033.1105900-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch fixes all following ICE in zve64d: FAIL: gcc.dg/vect/pr71259.c -flto -ffat-lto-objects (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/pr71259.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-14.c (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-alias-check-14.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-14.c -flto -ffat-lto-objects (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-alias-check-14.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-9.c (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-alias-check-9.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-9.c -flto -ffat-lto-objects (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-alias-check-9.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-cond-arith-6.c (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-cond-arith-6.c (test for excess errors) FAIL: gcc.dg/vect/vect-cond-arith-6.c -flto -ffat-lto-objects (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-cond-arith-6.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-gather-5.c (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-gather-5.c (test for excess errors) FAIL: gcc.dg/vect/vect-gather-5.c -flto -ffat-lto-objects (internal compiler error: in SET_TYPE_VECTOR_SUBPARTS, at tree.h:4248) FAIL: gcc.dg/vect/vect-gather-5.c -flto -ffat-lto-objects (test for excess errors) poly size (1, 1) vectors can not be allowed to interleave VLA SLP since interleave VLA SLP suppose VF at least hold 2 elements, whereas, poly size (1,1) may possible only have 1 element. PR target/112694 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_perm_const): Disallow poly size (1, 1) VLA SLP. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112694-2.c: New test. * gcc.target/riscv/rvv/autovec/pr112694-3.c: New test. --- gcc/config/riscv/riscv-v.cc | 9 +++++ .../gcc.target/riscv/rvv/autovec/pr112694-2.c | 35 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/pr112694-3.c | 37 +++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-3.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 983c037a4d4..588c127343e 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3364,6 +3364,15 @@ expand_vec_perm_const (machine_mode vmode, machine_mode op_mode, rtx target, mask to do the iteration loop control. Just disable it directly. */ if (GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL) return false; + /* FIXME: Explicitly disable VLA interleave SLP vectorization when we + may encounter ICE for poly size (1, 1) vectors in loop vectorizer. + Ideally, middle-end loop vectorizer should be able to disable it + itself, We can remove the codes here when middle-end code is able + to disable VLA SLP vectorization for poly size (1, 1) VF. */ + if (!BYTES_PER_RISCV_VECTOR.is_constant () + && maybe_lt (BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL, + poly_int64 (16, 16))) + return false; struct expand_vec_perm_d d; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-2.c new file mode 100644 index 00000000000..b99cd45ed74 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvfh_zfh -mabi=lp64d -O3 -fno-vect-cost-model" } */ + +long a[100], b[100], c[100]; + +void g1 () +{ + for (int i = 0; i < 100; i += 2) + { + c[i] += a[b[i]] + 1; + c[i + 1] += a[b[i + 1]] + 2; + } +} + +long g2 () +{ + long res = 0; + for (int i = 0; i < 100; i += 2) + { + res += a[b[i + 1]]; + res += a[b[i]]; + } + return res; +} + +long g3 () +{ + long res = 0; + for (int i = 0; i < 100; i += 2) + { + res += a[b[i]]; + res += a[b[i + 1]]; + } + return res; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-3.c new file mode 100644 index 00000000000..d65488bb94c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-3.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve64d_zvfh_zfh -mabi=lp64d -fdiagnostics-plain-output -flto -ffat-lto-objects -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O3" } */ + +#define VECTOR_BITS 512 +#define N (VECTOR_BITS * 11 / 64 + 4) + +#define add(A, B) ((A) + (B)) + +#define DEF(OP) \ + void __attribute__ ((noipa)) \ + f_##OP (double *restrict a, double *restrict b, double x) \ + { \ + for (int i = 0; i < N; i += 2) \ + { \ + a[i] = b[i] < 100 ? OP (b[i], x) : b[i]; \ + a[i + 1] = b[i + 1] < 70 ? OP (b[i + 1], x) : b[i + 1]; \ + } \ + } + +#define TEST(OP) \ + { \ + f_##OP (a, b, 10); \ + _Pragma("GCC novector") \ + for (int i = 0; i < N; ++i) \ + { \ + int bval = (i % 17) * 10; \ + int truev = OP (bval, 10); \ + if (a[i] != (bval < (i & 1 ? 70 : 100) ? truev : bval)) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +#define FOR_EACH_OP(T) \ + T (add) \ + +FOR_EACH_OP (DEF) -- 2.36.3