From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by sourceware.org (Postfix) with ESMTPS id 2883D3882ACB for ; Tue, 28 Nov 2023 13:16:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2883D3882ACB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2883D3882ACB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::336 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701177401; cv=none; b=QdeA0hUOlQoVsMJ81DqexKKwcQ/m7hbRvIHcrYndCasdObp1OG1mZwuahPqT+Th7lJtpzLe9/WGe09d5qYaeFW+nx7aN5j1mCnBAraBmkmGDxGrRcMxtxvR5/VFpD9aZW7kAtXtWItMF0j1KzSPrWkKqhGlhRiFzqK6R2CVRXDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701177401; c=relaxed/simple; bh=c4g4L1HVhcEx4voUgNdEp7OXmXsxQctK1+PTGIAwy0I=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=vGzes+7j6rcFJJm8bR6ZKAKaUvULsCLvjwX88y2X6HtaGiHHMC4/Acxxc5lm+5FWQHYfEdKl5lv7RpRJuPU1kl8ZaSBVc4XRITXU/NZ4EXxVTlcP0lcstge1pCkaZRmT9OhVbowFRUnyJpGAz1IAK8dCIlFttPWTBbtTI0RjFak= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40b4f60064eso3106965e9.1 for ; Tue, 28 Nov 2023 05:16:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1701177398; x=1701782198; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=Luy1eXz2BwgTlVdg6hrto+1vpHrIQ+RDujfPHk3esIUF0Qng5QUihfd1fOm6L4M0AN +YXL5XlAuJq7UkYEXlD1wBmIyNVLWkFDofByyirW2vZqwbcN4aX93G2EMz00E9QoS1wG lWOvx4OrLtd6iNc6+W5oe4Cwqb+sG1vsJ0kBO+j0JmCwx1CRiocZp9eZos/cIWodV0gP LzcQBpZ99FIhdv336QvDso3m/UxojKKsaPU9TTlNQgSbgzJdpSt11vr9EIy3wrnUxcnB Gl5AIprM+Khz4qUy+y6ibecQ3ynYvU5emWxJRtSEEjkc2MIIeW9x3Jk9fQ9BXgvnrZGm N2uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701177398; x=1701782198; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=teJZZ0ZOsZ+HGpSafZfJuL0JHURpiVfcB4slpxNMPBR7fsF/0lCEgJg1TmrMkQ29pr kt9VC1XPImpWljVfdB/5e4JA4/hWT8DSXKeQjKFyUVWNWSqelddo47+k4+dW6DnIWIVx XW/tSkUU3xATywouI7cmz5K3h+fCZzwwaESVledf2MJ+1cymc0hcvu8FTGQFhR5oyBtU OOhHu/q91WcIGPyLCckdIV8BTEWDOaB1B+005qUDA55AC+moVZDFuXWk/oaXyJpv+GPN HewEJjoSJhEw3M13LRfZDgQdV9FX1kKwlWLUP8JUdMA40bl8jhths/oK7whXTXuy+Lv3 JN9w== X-Gm-Message-State: AOJu0Yw5f7oLqiN1P2eRampqogZYr0GdX3/lLamwyXGxyUoeVHUTBhs/ 0MLAGqipaQkvn3YXcCIX+w+Ndwq8GY7JbIORG6iseA== X-Google-Smtp-Source: AGHT+IHasFp6UvoHyLMnVrlIzOEYf3rsq0NWZ/DTJHnrPfKbJSj97uQRLNBj3LwdJWF2gLX+VsLSRw== X-Received: by 2002:a05:600c:1d04:b0:40b:4ff7:7547 with SMTP id l4-20020a05600c1d0400b0040b4ff77547mr372209wms.0.1701177398553; Tue, 28 Nov 2023 05:16:38 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id s9-20020a05600c45c900b0040b3829eb50sm15991844wmo.20.2023.11.28.05.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 05:16:37 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Tue, 28 Nov 2023 13:16:14 +0000 Message-Id: <20231128131615.3986922-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128131615.3986922-1-mary.bennett@embecosm.com> References: <20231113133530.1727444-1-mary.bennett@embecosm.com> <20231128131615.3986922-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index c7a2ba07bcc..92bf0b5d6a6 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" -- 2.34.1