From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 4773238582BE for ; Sat, 2 Dec 2023 08:14:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4773238582BE Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4773238582BE Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701504899; cv=none; b=v/wlUEQs41cMMbExumEhPkqFmZij34XjmQGHGzwEAix00g564GcDS7sKePB24V3Dti0SpNKp/Zhc/Aw5Mmyd7ueocHXprWIrbFGEf2RIXbcgMugitUWvu1hKAICmDzm5IE/zqCwTjNyG2mb/jzXH+kOEHNRyQOxy2oB0fCSUKTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701504899; c=relaxed/simple; bh=TcdU+yhIk9Bk55nH/VtGoBuYw2996KkdQcCQHdSmtp8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZsHQ0clmpWjrjww4BZBjKIGq4SpFU+Jv37ZkCmxuBEJopnqJo4yztoX5tEjxaIGkeitOXJsKET8xUeDuTIwKPknk6hjZqoB3YO6YYsGhrfsU0+hrer0LXWLTI09QKNIJDOJWVg1A7iVhYnL7amgbZJR7aIpvZmhD8YAqLtmT7Y8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Cx2ep652pl+lw+AA--.53348S3; Sat, 02 Dec 2023 16:14:50 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxzt5y52pljlZSAA--.53266S4; Sat, 02 Dec 2023 16:14:47 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v1 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code. Date: Sat, 2 Dec 2023 16:14:41 +0800 Message-Id: <20231202081441.4799-3-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231202081441.4799-1-chenglulu@loongson.cn> References: <20231202081441.4799-1-chenglulu@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8Cxzt5y52pljlZSAA--.53266S4 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWfGr1xZF1kGFWUCF4fWr4rJFc_yoWDtw15pF 9ruwsxtr48GrsxWr4Dt3s5WwnrJ3srKr12qF1ftF18Ca17Xr18ZF48GFZxXF1jqa9Yqry2 qryFkw43Za1jkacCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAF wI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8P5r7UUUUU== X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The instructions defined in LoongArch Reference Manual v1.1 are not the instruction set v1.1 version. The CPU defined later may only support some instructions in LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and related definitions are removed here. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro. (fill_native_cpu_config): Define a new variable hw_isa_evolution record the extended instruction set support read from cpucfg. * config/loongarch/loongarch-def.cc: Set evolution at initialization. * config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete. (ISA_BASE_LA64V110): Likewise. (N_ISA_BASE_TYPES): Likewise. (defined): Likewise. * config/loongarch/loongarch-opts.cc: Likewise. * config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise. (ISA_BASE_IS_LA64V110): Likewise. * config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise. * config/loongarch/loongarch.opt: Regenerate. --- .../loongarch/genopts/loongarch-strings | 1 - gcc/config/loongarch/genopts/loongarch.opt.in | 3 --- gcc/config/loongarch/loongarch-cpu.cc | 23 +++++-------------- gcc/config/loongarch/loongarch-def.cc | 14 +++++++---- gcc/config/loongarch/loongarch-def.h | 12 ++-------- gcc/config/loongarch/loongarch-opts.cc | 3 --- gcc/config/loongarch/loongarch-opts.h | 4 +--- gcc/config/loongarch/loongarch-str.h | 1 - gcc/config/loongarch/loongarch.opt | 3 --- 9 files changed, 19 insertions(+), 45 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index b2070c83ed0..7bc4824007e 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -30,7 +30,6 @@ STR_CPU_LA664 la664 # Base architecture STR_ISA_BASE_LA64V100 la64 -STR_ISA_BASE_LA64V110 la64v1.1 # -mfpu OPTSTR_ISA_EXT_FPU fpu diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 8af6cc6f532..483b185b059 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -32,9 +32,6 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) -EnumValue -Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110) - ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index 622df47916f..4033320d0e1 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -23,7 +23,6 @@ along with GCC; see the file COPYING3. If not see #include "config.h" #include "system.h" #include "coretypes.h" -#include "tm.h" #include "diagnostic-core.h" #include "loongarch-def.h" @@ -32,19 +31,6 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-cpucfg-map.h" #include "loongarch-str.h" -/* loongarch_isa_base_features defined here instead of loongarch-def.c - because we need to use options.h. Pay attention on the order of elements - in the initializer becaue ISO C++ does not allow C99 designated - initializers! */ - -#define ISA_BASE_LA64V110_FEATURES \ - (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \ - | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS) - -int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { - /* [ISA_BASE_LA64V100] = */ 0, - /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES, -}; /* Native CPU detection with "cpucfg" */ static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 }; @@ -235,18 +221,20 @@ fill_native_cpu_config (struct loongarch_target *tgt) /* Use the native value anyways. */ preset.simd = tmp; + + int64_t hw_isa_evolution = 0; + /* Features added during ISA evolution. */ for (const auto &entry: cpucfg_map) if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit) - preset.evolution |= entry.isa_evolution_bit; + hw_isa_evolution |= entry.isa_evolution_bit; if (native_cpu_type != CPU_NATIVE) { /* Check if the local CPU really supports the features of the base ISA of probed native_cpu_type. If any feature is not detected, either GCC or the hardware is buggy. */ - auto base_isa_feature = loongarch_isa_base_features[preset.base]; - if ((preset.evolution & base_isa_feature) != base_isa_feature) + if ((preset.evolution & hw_isa_evolution) != hw_isa_evolution) warning (0, "detected base architecture %qs, but some of its " "features are not detected; the detected base " @@ -254,6 +242,7 @@ fill_native_cpu_config (struct loongarch_target *tgt) "features will be enabled", loongarch_isa_base_strings[preset.base]); } + preset.evolution = hw_isa_evolution; } if (tune_native_p) diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc index 6990c86c2c4..bc6997e45b5 100644 --- a/gcc/config/loongarch/loongarch-def.cc +++ b/gcc/config/loongarch/loongarch-def.cc @@ -18,6 +18,11 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" + #include "loongarch-def.h" #include "loongarch-str.h" @@ -51,9 +56,11 @@ array_arch loongarch_cpu_default_isa = .simd_ (ISA_EXT_SIMD_LASX)) .set (CPU_LA664, loongarch_isa () - .base_ (ISA_BASE_LA64V110) + .base_ (ISA_BASE_LA64V100) .fpu_ (ISA_EXT_FPU64) - .simd_ (ISA_EXT_SIMD_LASX)); + .simd_ (ISA_EXT_SIMD_LASX) + .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA + | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)); static inline loongarch_cache la464_cache () { @@ -136,8 +143,7 @@ array_tune loongarch_cpu_multipass_dfa_lookahead = array_tune () array loongarch_isa_base_strings = array () - .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100) - .set (ISA_BASE_LA64V110, STR_ISA_BASE_LA64V110); + .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100); array loongarch_isa_ext_strings = array () diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 0603b9b821d..1bf2b27470d 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -56,19 +56,11 @@ along with GCC; see the file COPYING3. If not see /* enum isa_base */ /* LoongArch V1.00. */ -#define ISA_BASE_LA64V100 0 -/* LoongArch V1.10. */ -#define ISA_BASE_LA64V110 1 -#define N_ISA_BASE_TYPES 2 +#define ISA_BASE_LA64V100 0 +#define N_ISA_BASE_TYPES 1 extern loongarch_def_array loongarch_isa_base_strings; -#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) -/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is - we cannot use the C++ header options.h in loongarch-def.c. */ -extern int64_t loongarch_isa_base_features[]; -#endif - /* enum isa_ext_* */ #define ISA_EXT_NONE 0 #define ISA_EXT_FPU32 1 diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 6861642a98d..d52a0966b58 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -285,9 +285,6 @@ config_target_isa: /* Get default ISA from "-march" or its default value. */ t.isa = loongarch_cpu_default_isa[t.cpu_arch]; - if (t.cpu_arch != CPU_NATIVE) - t.isa.evolution |= loongarch_isa_base_features[t.isa.base]; - /* Apply incremental changes. */ /* "-march=native" overrides the default FPU type. */ diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index 7a644c86d48..8eee393e3eb 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -79,8 +79,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) #define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) -#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \ - || la_target.isa.base == ISA_BASE_LA64V110) +#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) @@ -92,7 +91,6 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) #define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664) -#define ISA_BASE_IS_LA64V110 (la_target.isa.base == ISA_BASE_LA64V110) /* Note: optimize_size may vary across functions, while -m[no]-memcpy imposes a global constraint. */ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 0384493765c..7c78d1443d5 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -33,7 +33,6 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_LA664 "la664" #define STR_ISA_BASE_LA64V100 "la64" -#define STR_ISA_BASE_LA64V110 "la64v1.1" #define OPTSTR_ISA_EXT_FPU "fpu" #define STR_NONE "none" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 4d36e3ec4de..41e6424e861 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -40,9 +40,6 @@ Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100) -EnumValue -Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110) - ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) -- 2.31.1