Re: Re: [PATCH 1/7] RISC-V: Add intrinsic functions for crypto vector Zvbb extension

["Feng Wang" <wangfeng@eswincomputing.com>]

2023-12-04 16:01 Kito Cheng <kito.cheng@gmail.com> wrote:



>Hi Feng:
>
>Thanks for the patch! a few inline comments below, also don't include
>all test files from doc generator, only include a few within the patch
>is fine, e.g. pick one for each group, so that it won't make GCC
>source tree bloat too much.
>

OK. All the test cases are indeed too large, will be reduced.


>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index 935eeb7fd8e..2a3777e168c 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -428,6 +428,15 @@
>> ;; vcompress vector compress instruction
>> ;; vmov whole vector register move
>> ;; vector unknown vector instruction
>> +;; vandn crypto vector bitwise and-not instructions
>> +;; vbrev crypto vector reverse bits in elements instructions
>> +;; vbrev8 crypto vector reverse bits in bytes instructions
>> +;; vrev8 crypto vector reverse bytes instructions
>> +;; vclz crypto vector count leading Zeros instructions
>> +;; vctz crypto vector count lrailing Zeros instructions
>> +;; vrol crypto vector rotate left instructions
>> +;; vror crypto vector rotate right instructions
>
>Use vialu for above operations, no new type for those instructions.
>
>> +;; vwsll crypto vector widening shift left logical instructions
>
>Rename to vwshift to make it consistent with vnshift.
>
>> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
>> new file mode 100755
>> index 00000000000..0373cf6f48a
>> --- /dev/null
>> +++ b/gcc/config/riscv/vector-crypto.md
>> @@ -0,0 +1,207 @@
>> +(define_c_enum "unspec" [
>> + ;; Zvbb unspecs
>> + UNSPEC_VANDN
>> + UNSPEC_VBREV
>> + UNSPEC_VBREV8
>> + UNSPEC_VREV8
>> + UNSPEC_VCLZ
>> + UNSPEC_VCTZ
>> + UNSPEC_VROL
>> + UNSPEC_VROR
>> + UNSPEC_VWSLL
>> +])
>
>Could you use generic RTL code for andn, clz, ctl, rol, ror and wsll
>rather than unspec?


Got it! will optimize it., thanks!
Feng Wang