From: Feng Wang <wangfeng@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, jeffreyalaw@gmail.com,
juzhe.zhong@rivai.ai, zhusonghe@eswincomputing.com,
panciyan@eswincomputing.com,
Feng Wang <wangfeng@eswincomputing.com>
Subject: [PATCH 1/4] RISC-V: Add crypto vector implied ISA info.
Date: Wed, 6 Dec 2023 02:45:21 +0000 [thread overview]
Message-ID: <20231206024524.10792-1-wangfeng@eswincomputing.com> (raw)
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
---
gcc/common/config/riscv/riscv-common.cc | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6c210412515..dbb42ca2f1e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksc", "zvbc"},
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zvbb", "zvkb"},
+ {"zvbc", "v"},
+ {"zvkb", "v"},
+ {"zvkg", "v"},
+ {"zvkned", "v"},
+ {"zvknha", "v"},
+ {"zvknhb", "v"},
+ {"zvksed", "v"},
+ {"zvksh", "v"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
--
2.17.1
next reply other threads:[~2023-12-06 2:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 2:45 Feng Wang [this message]
2023-12-06 2:45 ` [PATCH 2/4] RISC-V: Add crypto vector builtin function Feng Wang
2023-12-06 6:45 ` juzhe.zhong
2023-12-06 2:45 ` [PATCH 3/4] RISC-V: Add crypto vector machine descriptions Feng Wang
2023-12-06 6:53 ` juzhe.zhong
2023-12-07 2:13 ` Feng Wang
2023-12-06 2:45 ` [PATCH 4/4] RISC-V: Add crypto vector api-testing cases Feng Wang
2023-12-06 3:33 ` [PATCH 1/4] RISC-V: Add crypto vector implied ISA info Tsukasa OI
2023-12-07 2:15 ` Feng Wang
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