From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 033253858D38 for ; Wed, 6 Dec 2023 14:26:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 033253858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 033253858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.207.19.206 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701872822; cv=none; b=Osb0ehcpiFc3G6OSYi38nzAF7Nb3rNx/NLbzreDd3HudAqYk/NHLg+abkpDRttkatBvcWo5BwZsFdQO16WtkdnN3rgv/8YuXc78odPKciw9AODMx1sfFkZCQSMi5bSs38/40Ifa7hPKFXgMmp3Wx1ipc/Kk8GHlUgG/9EYAzecY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701872822; c=relaxed/simple; bh=na/bJ9BIYEuDWA/Sx9syAugGN9HR6UX0i3nhw2+BB1w=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=it3+xDzYJxlDulFD5eFuwuL+JMihLBBGFQaeVZAmB0iOgGrd+9a6X4VetJ46BqH1eXPopd2R414h9OJ1cg7Iiz8/IB4M5wvubq1Rb3QYmNSAlGWKTST1/k5P+Rrox0BIEFaRbUjYQ46ClNmrBAqPbLZaIIkfJ+8JyhnrIcrdzLQ= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp86t1701872808t0u6s1rd Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 06 Dec 2023 22:26:47 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: cvpDInk2tjWONZPcZHD1aJQcbc7qEwtMk2LHYAUbYMj+/1jQXOhDnM+l9l1rr GjPWGL5IIGTCfjpoeWsiu2gYI+RK2tWLcvac5er2WE95RjoUnFiGDepqT1DLP5TNW/Kt6jC e6p2cUTQg+YpnoalbXPBFUCO+8M+4z1/FNQ31oWBJZ78SlwHaO2Z0waWv8oDDOz45TdGPP4 8oMmL3HrQonUkfimIMtmagf8hRRTCaOJL6vS5wEwBoJOAmOBRwefyUHFA6HbCrJ7lskL3wT y3LKVmz+YDrN82DJ2EVf7l7Vg3LbbM4rYXNiMfEhfHZlS+V6TWlf+0+sklnextqGXY83dtA FS1BB0nqPfTgb8sygYIS9VL15VY4o3qmhs6KsbIaa1qfF+1PztXIkrnzvZaPOhDQ99eU1qG X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3768400233759309561 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed V2] RISC-V: Fix VSETVL PASS bug Date: Wed, 6 Dec 2023 22:26:46 +0800 Message-Id: <20231206142646.3402479-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: As PR112855 mentioned, the VSETVL PASS insert vsetvli in unexpected location. Due to 2 reasons: 1. incorrect transparant computation LCM data. We need to check VL operand defs and uses. 2. incorrect fusion of unrelated edge which is the edge never reach the vsetvl expression. PR target/112855 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix transparant LCM data. (pre_vsetvl::earliest_fuse_vsetvl_info): Disable earliest fusion for unrelated edge. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112855.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 66 ++++++++++++++++++- .../gcc.target/riscv/rvv/autovec/pr112855.c | 26 ++++++++ 2 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112855.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 484a8b3a514..68f0be7e81d 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2034,7 +2034,7 @@ private: gcc_unreachable (); } - bool anticpatable_exp_p (const vsetvl_info &header_info) + bool anticipated_exp_p (const vsetvl_info &header_info) { if (!header_info.has_nonvlmax_reg_avl () && !header_info.has_vl ()) return true; @@ -2645,7 +2645,7 @@ pre_vsetvl::compute_lcm_local_properties () } } - for (const insn_info *insn : bb->real_nondebug_insns ()) + for (insn_info *insn : bb->real_nondebug_insns ()) { if (info.has_nonvlmax_reg_avl () && find_access (insn->defs (), REGNO (info.get_avl ()))) @@ -2653,6 +2653,59 @@ pre_vsetvl::compute_lcm_local_properties () bitmap_clear_bit (m_transp[bb_index], i); break; } + + if (info.has_vl () + && reg_mentioned_p (info.get_vl (), insn->rtl ())) + { + if (find_access (insn->defs (), REGNO (info.get_vl ()))) + /* We can't fuse vsetvl into the blocks that modify the + VL operand since successors of such blocks will need + the value of those blocks are defining. + + bb 4: def a5 + / \ + bb 5:use a5 bb 6:vsetvl a5, 5 + + The example above shows that we can't fuse vsetvl + from bb 6 into bb 4 since the successor bb 5 is using + the value defined in bb 4. */ + ; + else + { + /* We can't fuse vsetvl into the blocks that use the + VL operand which has different value from the + vsetvl info. + + bb 4: def a5 + | + bb 5: use a5 + | + bb 6: def a5 + | + bb 7: use a5 + + The example above shows that we can't fuse vsetvl + from bb 6 into bb 5 since their value is different. + */ + resource_info resource + = full_register (REGNO (info.get_vl ())); + def_lookup dl = crtl->ssa->find_def (resource, insn); + def_info *def + = dl.matching_set_or_last_def_of_prev_group (); + gcc_assert (def); + insn_info *def_insn = extract_single_source ( + dyn_cast (def)); + if (def_insn && vsetvl_insn_p (def_insn->rtl ())) + { + vsetvl_info def_info = vsetvl_info (def_insn); + if (m_dem.compatible_p (def_info, info)) + continue; + } + } + + bitmap_clear_bit (m_transp[bb_index], i); + break; + } } } @@ -2663,7 +2716,7 @@ pre_vsetvl::compute_lcm_local_properties () vsetvl_info &footer_info = block_info.get_exit_info (); if (header_info.valid_p () - && (anticpatable_exp_p (header_info) || block_info.full_available)) + && (anticipated_exp_p (header_info) || block_info.full_available)) bitmap_set_bit (m_antloc[bb_index], get_expr_index (m_exprs, header_info)); @@ -2920,6 +2973,13 @@ pre_vsetvl::earliest_fuse_vsetvl_info () || eg->dest == EXIT_BLOCK_PTR_FOR_FN (cfun)) continue; + /* When multiple set bits in earliest edge, such edge may + have infinite loop in preds or succs or multiple conflict + vsetvl expression which make such edge is unrelated. We + don't perform fusion for such situation. */ + if (bitmap_count_bits (e) != 1) + continue; + vsetvl_block_info &src_block_info = get_block_info (eg->src); vsetvl_block_info &dest_block_info = get_block_info (eg->dest); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112855.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112855.c new file mode 100644 index 00000000000..f1fa6693d2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112855.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-require-effective-target riscv_v } */ + +#include +int a; +int b = 100; +int c[25]; +int d; +int main() { + int e; + d = 0; + for (; d < 5; d++) { + e = 0; + for (; e < 5; e++) + c[d * 5 + e] = 0; + } + if (b) + if (a) + for (;;) + ; + b++; + int volatile f = *c; + assert(b == 101); +} -- 2.36.3