From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id 372D53858288 for ; Thu, 7 Dec 2023 10:17:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 372D53858288 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 372D53858288 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701944265; cv=none; b=Erj7OyyVfIaaCEWi7cW/PVe+VovWkdpETg8kkQOYMBKkiucjDtJwfZC7dZ/STIQ40wbjzY/usyIEuzE9uq50znFNVvIFRQzI62BihdJP0zR7LZLxqkgXnZZivNWxM/Tvt5ONmLzYC+vrF5zeeh7oz9deL7O1uki1bsRBz71FoS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701944265; c=relaxed/simple; bh=SlNNNcamszmOc5np3tb2OUz4SkbTH0ANpyomuuWF4KM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=QjFZ4w3hhNIoiMWVv43XwfZJi4xSLle4boHZUPMz0VgTPbYkbq7pmDHkd6IGxBodZtrKP7rsCHHIZQh2FYf1I9QELJb/30P/S14hQGHkhB62c6nEiBNBiPtTdJIpfu02aRS+EQ4OLXRZIc5fhLY5vmndf/tNNoN2ZcfcGqbE0zQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [122.8.183.87]) by APP-01 (Coremail) with SMTP id qwCowADnyDHHmnFlwv3BAQ--.680S4; Thu, 07 Dec 2023 18:13:38 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: christoph.muellner@vrull.eu, kito.cheng@gmail.com, shiyulong@iscas.ac.cn, jiawei@iscas.ac.cn, chenyixuan@iscas.an.cn, jeffreyalaw@gmail.com, Liao Shihua Subject: [PATCH V2 2/2]RISC-V: Add C intrinsics of Bitmanip Extension Date: Thu, 7 Dec 2023 18:16:39 +0800 Message-Id: <20231207101639.3695340-3-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207101639.3695340-1-shihua@iscas.ac.cn> References: <20231207101639.3695340-1-shihua@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:qwCowADnyDHHmnFlwv3BAQ--.680S4 X-Coremail-Antispam: 1UD129KBjvAXoWfCw1UAr4UCw4xKw4DGF18AFb_yoW8ZF4kXo W0gr4rJ3W5G3W3uFsakw15Wr1qqFWkuayDZayrZFW5KFn3Cwnakr45tw1DAF10qrW3AF15 Zas2qr4fJa17C34fn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYZ7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42xK82 IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC2 0s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMI IF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF 0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87 Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU8yCGUUUUU X-Originating-IP: [122.8.183.87] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAxASEWVxhWliqQAAsj X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch adds C intrinsics for Bitmanip Extension. RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN. But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN. gcc/ChangeLog: * config.gcc: Add riscv_bitmanip.h * config/riscv/riscv-builtins.cc (AVAIL): New AVAIL. (RISCV_BUILTIN_NO_PREFIX): new riscv_builtin_description. * config/riscv/riscv-ftypes.def (2): New function type. * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN_NO_PREFIX):New builtins. * config/riscv/riscv_bitmanip.h: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test. * gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test. --- gcc/config.gcc | 2 +- gcc/config/riscv/riscv-builtins.cc | 22 ++ gcc/config/riscv/riscv-ftypes.def | 2 + gcc/config/riscv/riscv-scalar-crypto.def | 18 ++ gcc/config/riscv/riscv_bitmanip.h | 297 ++++++++++++++++++ .../riscv/scalar_bitmanip_intrinsic-32.c | 97 ++++++ .../riscv/scalar_bitmanip_intrinsic-64.c | 115 +++++++ 7 files changed, 552 insertions(+), 1 deletion(-) create mode 100644 gcc/config/riscv/riscv_bitmanip.h create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c diff --git a/gcc/config.gcc b/gcc/config.gcc index d67fe8b6a6f..37e66143c53 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -548,7 +548,7 @@ riscv*) extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" extra_objs="${extra_objs} thead.o riscv-target-attr.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h riscv_crypto.h" + extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" ;; diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index fc3976f3ba1..3a297b3742e 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -123,6 +123,12 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT) AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT) AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT) AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT) +AVAIL (zbb, TARGET_ZBB) +AVAIL (zbb32, TARGET_ZBB && !TARGET_64BIT) +AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT) +AVAIL (zbb32_or_zbkb32, (TARGET_ZBKB || TARGET_ZBB) && !TARGET_64BIT) +AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT) +AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB)) AVAIL (hint_pause, (!0)) // CORE-V AVAIL @@ -145,6 +151,22 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME, \ BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL } +/* Construct a riscv_builtin_description from the given arguments like RISCV_BUILTIN. + + INSN is the name of the associated instruction pattern, without the + leading CODE_FOR_. + + NAME is the name of the function itself, without the leading + "__builtin_riscv_". + + BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields. + + AVAIL is the name of the availability predicate, without the leading + riscv_builtin_avail_. */ +#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL) \ + { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME, \ + BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL } + /* Define __builtin_riscv_, which is a RISCV_BUILTIN_DIRECT function mapped to instruction CODE_FOR_riscv_, FUNCTION_TYPE and AVAIL are as for RISCV_BUILTIN. */ diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 0d1e4dd061e..13221090e5f 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -39,9 +39,11 @@ DEF_RISCV_FTYPE (1, (SI, HI)) DEF_RISCV_FTYPE (2, (USI, UQI, UQI)) DEF_RISCV_FTYPE (2, (USI, UHI, UHI)) DEF_RISCV_FTYPE (2, (USI, USI, USI)) +DEF_RISCV_FTYPE (2, (USI, USI, UQI)) DEF_RISCV_FTYPE (2, (UDI, UQI, UQI)) DEF_RISCV_FTYPE (2, (UDI, UHI, UHI)) DEF_RISCV_FTYPE (2, (UDI, USI, USI)) +DEF_RISCV_FTYPE (2, (UDI, UDI, UQI)) DEF_RISCV_FTYPE (2, (UDI, UDI, USI)) DEF_RISCV_FTYPE (2, (UDI, UDI, UDI)) DEF_RISCV_FTYPE (2, (SI, USI, USI)) diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index 3db9ed4a03e..b1a71139d05 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -78,3 +78,21 @@ RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cry // ZKSED RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed), RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed), + + +// ZBB + +RISCV_BUILTIN_NO_PREFIX (clzsi2,"clz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb), +RISCV_BUILTIN_NO_PREFIX (clzdi2,"clz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64), +RISCV_BUILTIN_NO_PREFIX (ctzsi2,"ctz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb), +RISCV_BUILTIN_NO_PREFIX (ctzdi2,"ctz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64), +RISCV_BUILTIN_NO_PREFIX (popcountsi2,"popcount_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb), +RISCV_BUILTIN_NO_PREFIX (popcountdi2,"popcount_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64), +RISCV_BUILTIN_NO_PREFIX (orcbsi2,"orc_b_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb32), +RISCV_BUILTIN_NO_PREFIX (orcbdi2,"orc_b_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64), + +// ZBKB +RISCV_BUILTIN_NO_PREFIX (rotrsi3,"ror_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb), +RISCV_BUILTIN_NO_PREFIX (rotlsi3,"rol_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb), +RISCV_BUILTIN_NO_PREFIX (rotrdi3,"ror_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64), +RISCV_BUILTIN_NO_PREFIX (rotldi3,"rol_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64), diff --git a/gcc/config/riscv/riscv_bitmanip.h b/gcc/config/riscv/riscv_bitmanip.h new file mode 100644 index 00000000000..2c44396e482 --- /dev/null +++ b/gcc/config/riscv/riscv_bitmanip.h @@ -0,0 +1,297 @@ +/* RISC-V Bitmanip Extension intrinsics include file. + Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef __RISCV_BITMANIP_H +#define __RISCV_BITMANIP_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__riscv_zbb) + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clz_32 (uint32_t x) +{ + return __builtin_riscv_clz_32 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_ctz_32 (uint32_t x) +{ + return __builtin_riscv_ctz_32 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_cpop_32 (uint32_t x) +{ + return __builtin_riscv_popcount_32 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_orc_b_32 (uint32_t x) +{ + return __builtin_riscv_orc_b_32 (x); +} + +#if __riscv_xlen == 64 + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clz_64 (uint64_t x) +{ + return __builtin_riscv_clz_64 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_ctz_64 (uint64_t x) +{ + return __builtin_riscv_ctz_64 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_cpop_64 (uint64_t x) +{ + return __builtin_riscv_popcount_64 (x); +} + +extern __inline unsigned +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_orc_b_64 (uint64_t x) +{ + return __builtin_riscv_orc_b_64 (x); +} + +#endif + +#endif // __riscv_zbb + +#if defined (__riscv_zbb) || defined (__riscv_zbkb) + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_ror_32 (uint32_t x, uint32_t shamt) +{ + return __builtin_riscv_ror_32 (x,shamt); +} + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_rol_32 (uint32_t x, uint32_t shamt) +{ + return __builtin_riscv_rol_32 (x,shamt); +} + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_rev8_32 (uint32_t x) +{ + return __builtin_bswap32 (x); +} + +#if __riscv_xlen == 64 + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_ror_64 (uint64_t x, uint32_t shamt) +{ + return __builtin_riscv_ror_64 (x,shamt); +} + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_rol_64 (uint64_t x, uint32_t shamt) +{ + return __builtin_riscv_rol_64 (x,shamt); +} + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_rev8_64 (uint64_t x) +{ + return __builtin_bswap64 (x); +} + +#endif + +#endif // __riscv_zbb || __riscv_zbkb + +#if defined (__riscv_zbkb) + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_brev8_32 (uint32_t x) +{ + return __builtin_riscv_brev8 (x); +} + +#if __riscv_xlen == 32 + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_zip_32 (uint32_t x) +{ + return __builtin_riscv_zip (x); +} + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_unzip_32 (uint32_t x) +{ + return __builtin_riscv_unzip (x); +} + +#endif + +#if __riscv_xlen == 64 + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_brev8_64 (uint64_t x) +{ + return __builtin_riscv_brev8 (x); +} + +#endif + +#endif // __riscv_zbkb + +#if defined (__riscv_zbc) || defined (__riscv_zbkc) + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmul_32 (uint32_t rs1, uint32_t rs2) +{ + return __builtin_riscv_clmul (rs1,rs2); +} + +#if __riscv_xlen == 32 + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmulh_32 (uint32_t rs1, uint32_t rs2) +{ + return __builtin_riscv_clmulh (rs1,rs2); +} + +#endif + +#if __riscv_xlen == 64 + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmul_64 (uint64_t rs1, uint64_t rs2) +{ + return __builtin_riscv_clmul (rs1,rs2); +} + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmulh_64 (uint64_t rs1, uint64_t rs2) +{ + return __builtin_riscv_clmulh (rs1,rs2); +} + +#endif + +#endif // __riscv_zbc || __riscv_zbkc + +#if defined (__riscv_zbc) + +#if __riscv_xlen == 32 + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmulr_32 (uint32_t rs1, uint32_t rs2) +{ + return __builtin_riscv_clmulr (rs1,rs2); +} + +#endif + +#if __riscv_xlen == 64 + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_clmulr_64 (uint64_t rs1, uint64_t rs2) +{ + return __builtin_riscv_clmulr (rs1,rs2); +} + +#endif + +#endif // __riscv_zbc + +#if defined (__riscv_zbkx) + +#if __riscv_xlen == 32 + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_xperm4_32 (uint32_t rs1, uint32_t rs2) +{ + return __builtin_riscv_xperm4 (rs1,rs2); +} + +extern __inline uint32_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_xperm8_32 (uint32_t rs1, uint32_t rs2) +{ + return __builtin_riscv_xperm8 (rs1,rs2); +} + +#endif + +#if __riscv_xlen == 64 + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_xperm4_64 (uint64_t rs1, uint64_t rs2) +{ + return __builtin_riscv_xperm4 (rs1,rs2); +} + +extern __inline uint64_t +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__riscv_xperm8_64 (uint64_t rs1, uint64_t rs2) +{ + return __builtin_riscv_xperm8 (rs1,rs2); +} + +#endif + +#endif // __riscv_zbkx + +#if defined (__cplusplus) +} +#endif // __cplusplus +#endif // __RISCV_BITMANIP_H \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c new file mode 100644 index 00000000000..ab492c12b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_bitmanip.h" + +unsigned foo1(uint32_t x) +{ + return __riscv_clz_32(x); +} + +unsigned foo2(uint32_t x) +{ + return __riscv_ctz_32(x); +} + +unsigned foo3(uint32_t x) +{ + return __riscv_cpop_32(x); +} + +uint32_t foo4(uint32_t x) +{ + return __riscv_orc_b_32(x); +} + +uint32_t foo5(uint32_t x, uint32_t shamt) +{ + return __riscv_ror_32(x,shamt); +} + +uint32_t foo6(uint32_t x, uint32_t shamt) +{ + return __riscv_rol_32(x,shamt); +} + +uint32_t foo7(uint32_t x) +{ + return __riscv_rev8_32(x); +} + +uint32_t foo8(uint32_t x) +{ + return __riscv_brev8_32(x); +} + +uint32_t foo9(uint32_t x) +{ + return __riscv_zip_32(x); +} + +uint32_t foo10(uint32_t x) +{ + return __riscv_unzip_32(x); +} + +uint32_t foo11(uint32_t rs1,uint32_t rs2) +{ + return __riscv_clmul_32(rs1,rs2); +} + +uint32_t foo12(uint32_t rs1,uint32_t rs2) +{ + return __riscv_clmulh_32(rs1,rs2); +} + +uint32_t foo13(uint32_t rs1,uint32_t rs2) +{ + return __riscv_clmulr_32(rs1,rs2); +} + +uint32_t foo14(uint32_t rs1,uint32_t rs2) +{ + return __riscv_xperm4_32(rs1,rs2); +} + +uint32_t foo15(uint32_t rs1,uint32_t rs2) +{ + return __riscv_xperm8_32(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "clz" 1 } } */ +/* { dg-final { scan-assembler-times "ctz" 1 } } */ +/* { dg-final { scan-assembler-times "cpop" 1 } } */ +/* { dg-final { scan-assembler-times "orc.b" 1 } } */ +/* { dg-final { scan-assembler-times "ror" 1 } } */ +/* { dg-final { scan-assembler-times "rol" 1 } } */ +/* { dg-final { scan-assembler-times {\mrev8} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ +/* { dg-final { scan-assembler-times {\mzip} 1 } } */ +/* { dg-final { scan-assembler-times {\munzip} 1 } } */ +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c new file mode 100644 index 00000000000..caad74df518 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c @@ -0,0 +1,115 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_bitmanip.h" + +unsigned foo1(uint32_t x) +{ + return __riscv_clz_32(x); +} + +unsigned foo2(uint32_t x) +{ + return __riscv_ctz_32(x); +} + +unsigned foo3(uint32_t x) +{ + return __riscv_cpop_32(x); +} + +unsigned long foo4(uint32_t x, uint8_t shamt) +{ + return __riscv_ror_32(x,shamt); +} + +unsigned long foo5(uint32_t x, uint8_t shamt) +{ + return __riscv_rol_32(x,shamt); +} + +unsigned foo6(uint64_t x) +{ + return __riscv_clz_64(x); +} + +unsigned foo7(uint64_t x) +{ + return __riscv_ctz_64(x); +} + +unsigned foo8(uint64_t x) +{ + return __riscv_cpop_64(x); +} + +uint64_t foo9(uint64_t x) +{ + return __riscv_orc_b_64(x); +} + +uint64_t foo10(uint64_t rs1, uint8_t rs2) +{ + return __riscv_ror_64(rs1,rs2); +} + +uint64_t foo11(uint64_t rs1, uint8_t rs2) +{ + return __riscv_rol_64(rs1,rs2); +} + +uint64_t foo12(uint64_t x) +{ + return __riscv_rev8_64(x); +} + +uint64_t foo13(uint64_t x) +{ + return __riscv_brev8_64(x); +} + +uint64_t foo14(uint64_t rs1,uint64_t rs2) +{ + return __riscv_clmul_64(rs1,rs2); +} + +uint64_t foo15(uint64_t rs1,uint64_t rs2) +{ + return __riscv_clmulh_64(rs1,rs2); +} + +uint64_t foo16(uint64_t rs1,uint64_t rs2) +{ + return __riscv_clmulr_64(rs1,rs2); +} + +uint64_t foo17(uint64_t rs1,uint64_t rs2) +{ + return __riscv_xperm4_64(rs1,rs2); +} + +uint64_t foo18(uint64_t rs1,uint64_t rs2) +{ + return __riscv_xperm8_64(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "clzw" 1 } } */ +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-times "rorw" 1 } } */ +/* { dg-final { scan-assembler-times "rolw" 1 } } */ +/* { dg-final { scan-assembler-times "clz\t" 1 } } */ +/* { dg-final { scan-assembler-times "ctz\t" 1 } } */ +/* { dg-final { scan-assembler-times "cpop\t" 1 } } */ +/* { dg-final { scan-assembler-times "orc.b" 1 } } */ +/* { dg-final { scan-assembler-times "ror\t" 1 } } */ +/* { dg-final { scan-assembler-times "rol\t" 1 } } */ +/* { dg-final { scan-assembler-times {\mrev8} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ + -- 2.34.1