From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2050.outbound.protection.outlook.com [40.107.20.50]) by sourceware.org (Postfix) with ESMTPS id E1F71385AC12 for ; Thu, 7 Dec 2023 15:41:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1F71385AC12 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E1F71385AC12 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.20.50 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963686; cv=pass; b=hAWtvbYCP7milRupRx6ZqOT5A2vizby3IA0T7VWgeNTfwir2vjwP7eVCC6M/ukfoghrrjzhM7ZAduWTNnLwUawOMntjn1LjARH4ORZvKuimCv7k/9J4h3uSiLJCAtrP1skRX26rE0VeFxQWu3eXAgeZhXW+ETLDPtALW+O8QR/4= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1701963686; c=relaxed/simple; bh=tTPxj8MUm3V34M8CQfkFaLY2ZkBaHhkQtGf6omii85c=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=U6Tu4Jq453M+h1Q3RGDQdGaHJ2x1pY2EY9D81yfuC4o7zWW6VrweCfSL/sjjZZCt2V8ebeBj7FjLusPw7g9yDY2NVf974G46qmLJvLhW7nd7WuG4LG1sMy0s7lZHrnbpLysifNrlonWOW2O0uUeMFZcL/3zRV34NtWnw1fCFvxM= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=YlJki8gee2Z1YHtYjAJxk6qElin+sZfN8POFsAu11FGaRUd4h/g9cXdfY4CrGc9HGbMvlB4Xdu21WsN0aTIcv1ewdHExOCqx7hqakeySMqD8BDWDprjW1KV1eK3eFx0a9ss6d7mBrs2NvWRDbJ275gVw+7Xxc1YIprv/0UIqy+p5DSmzVPSFPXXF89T1IEIWMzhO3DujlI6zWUEmvaTaxQj28w+BBkqtY2pB0a6j5E8VuWcfR4qpH3Z7rX+y91vKiTS8HO902Rwc0HqQhFMBoHsImewSN6j1hi2icEUIoXhOTaJYdkf5mSgXMP3jkLUA6JGhvpZsIjivXEK+lhBwTw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=OOjBAX3mu/XUknKreLuHbHi5W0VNt0ZjhO1wr7EEmD0XK4QL/sDeZUGD87nPbobgL+8CVVCgS1iUPBeV9xpAwzmJyf6X19jeFQ3i3E9bsrR77LfrJQ2BCMERLS4eaZI0ZjeH3gLc7s1puLjecgIyRyi9SFufcrSNLEQrhWGoBgf+uOoD6MMmDuCAxM3CK+/scSXAtmRjiB1RMo8VfYcF8VEoXGYGG6pWOd9uLtMSPQifAVu9AL053VAYMBbu4SjQwc0gnKriAb22aJKvxaNnzSYv12f44oGDtyfIEM1wA5VEThRDOpHKH+rwnRX9jLjPlwv2KlUjXED0IqAwfF+ZGA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=yStPon+2An7JrakXr8jZcESslloE7wk9DW7BI7n3idkc3YwrFXdv1/8rXJ0KEtk41moVM3bRlXGu4SScAy81wQKOHfFTo9yTxj7z/QVEEh20BbpzmRmZwl3a8rCxSy68SYzLRLXf5hlvlUAcmnqzpLRl+/43THazEZIb5/2AX1k= Received: from DU2PR04CA0304.eurprd04.prod.outlook.com (2603:10a6:10:2b5::9) by DU0PR08MB7738.eurprd08.prod.outlook.com (2603:10a6:10:3be::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 15:41:20 +0000 Received: from DB5PEPF00014B96.eurprd02.prod.outlook.com (2603:10a6:10:2b5:cafe::fa) by DU2PR04CA0304.outlook.office365.com (2603:10a6:10:2b5::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B96.mail.protection.outlook.com (10.167.8.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:20 +0000 Received: ("Tessian outbound 5d213238733f:v228"); Thu, 07 Dec 2023 15:41:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: e8b47c3edc859f1d X-CR-MTA-TID: 64aa7808 Received: from 06908445bd28.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 51D2E2B7-4119-4305-8412-E7B4C0EE23AC.1; Thu, 07 Dec 2023 15:41:13 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 06908445bd28.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 07 Dec 2023 15:41:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aho/gEBvMR982x8rD8NKgxeM4OxY5Tedw6/Xq+b00IBHi3LZqaqmkAViX8OqQMenZHYtS+ty2Ot+oV9EQF7f+/AL/XywV0RxpL6lM6mD1+ezo0fwMH99gNQdP7cm4/LMF5WaSN4DypQttSAS2cKnR4UXAGpr++lLAbpwLwbkYleb5wUXbcg3qyUaIVFRn7KRmsiD0ZwdPRFyxmBbGNuNY4askhCUMV99MxIvPiEQYBszn3Ias7YXbgkY27cf/QI5tzA/LM6RC3i729DvzYJDol+uYy3tEE6cEtsKFgzBO/7ejQPqCXNLCV6+RqqvvUVk1/rZyc/qX4O5wr35U3y4XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=A8TVg+o30Q5BhtAVKCu9kIkRzBCDFSfM/SCCxdP2t+1POuo5Oo2hirm3m9SmFkztuvuHDDE4SjlUjF4QUzbE2IvDNQnOR2uEUs7vLCxj3LuHovirgysqVkH0r9g1qFJyMmLKBu31aJ7ZCISAw0jEEYXOnNjim7z719XN4IIw7UdWEUHuaLa8zE6xYkfMIATAKTlDxnzI1KR3x1kS2WNP+Nq4Xwv+VGMdcArryMh/1+zYh+YaIMeelp8ypQI5u48ytBpuhqkbw0s9RRSk+OMhouisNenW0+ntl3obx9QasY9uWphQ5M7UyqUu7ho2T03ABj4b3lkc3PzNTnjF+siCNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VeMOo49J0hxPyTnq9c8HzhfdZYI1cKvnVHlFj3BU334=; b=yStPon+2An7JrakXr8jZcESslloE7wk9DW7BI7n3idkc3YwrFXdv1/8rXJ0KEtk41moVM3bRlXGu4SScAy81wQKOHfFTo9yTxj7z/QVEEh20BbpzmRmZwl3a8rCxSy68SYzLRLXf5hlvlUAcmnqzpLRl+/43THazEZIb5/2AX1k= Received: from AS8PR04CA0172.eurprd04.prod.outlook.com (2603:10a6:20b:331::27) by DU0PR08MB9822.eurprd08.prod.outlook.com (2603:10a6:10:445::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.25; Thu, 7 Dec 2023 15:41:09 +0000 Received: from AMS0EPF000001B4.eurprd05.prod.outlook.com (2603:10a6:20b:331:cafe::40) by AS8PR04CA0172.outlook.office365.com (2603:10a6:20b:331::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF000001B4.mail.protection.outlook.com (10.167.16.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7068.20 via Frontend Transport; Thu, 7 Dec 2023 15:41:08 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 7 Dec 2023 15:41:07 +0000 Received: from e127754.cambridge.arm.com (10.1.34.67) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 7 Dec 2023 15:41:07 +0000 From: To: CC: Subject: [PATCH v2 2/3] [GCC] arm: vld1_types_x3 ACLE intrinsics Date: Thu, 7 Dec 2023 15:41:05 +0000 Message-ID: <20231207154106.4808-3-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231207154106.4808-1-Ezra.Sitorus@arm.com> References: <20231207154106.4808-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B4:EE_|DU0PR08MB9822:EE_|DB5PEPF00014B96:EE_|DU0PR08MB7738:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c9a05cf-a0e1-4ea6-222b-08dbf73af564 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: s1e2nSUlBBp/xb2t7N5ghe9s+orxS/E/04J87leMOLPAakQFPrvHjkgJ/ijIFBnnFYM2P7d20DBv+DZ4tqtcSe0fzAZZwPhSAe4OvDPPXizCS63x1wJNNvpQzJDrpCx88/odJa+VbLxe0VapVLn7KZ+F3b3HLAAWu0zwpCINYfV8udTYJKeRFKdozujNiR+J8fX2HyiqK7WZhmWsJ3oq4ocnGiXgQH5631Z0Id5XRHA9N26T8tE9/vIdu10CaRFe/R80yMmbJacthp59E4Q9FGoZSA+gxcViQPgbnpECCrkK+WOQZPTowamv2RU6pARlzl0KAz3sp8T4PDoXwa+slvfjZRv9cMiQhbFR4LZC3C0W186HNzTcOa36dHwfMB35pdnoM0hbDNDGx24caCz4FfvWOcYOBV/8JHaZlsGqCF/8qQOcEVHGw9ijo179ajU9tRYv63axq0QHYB8Zcjx4EJTfRyo9YmajrW9Qd2Dbph6G7778HKas1up7n50OpSeQQ/UdaSPnrdR+U76F/Em0Ry899KwhMwygXSAw2AQme1iGKoAUpNqtfWUZBccbEvips4PEDdZoULVhMwpCahb4fT4X2hjTkKxWil2resSKKhD2YGWyBDG1JUAm/wQegmeXRKpTaVqfRi29UjxPBBjs73gleEkgQkNrrddy1thIV7z0/dFo+oT3Z71c3Lerv7/RHQtfmnErTWGOiJtq7VRCoWeQBwFoT+nHpWE1iXEbdyrOelERf8jp7V9quID1fSsvZrVYxmHfgc2iQQls8nEl590cjCwcNkxWbgUTczz0YQ4= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(39860400002)(346002)(396003)(230922051799003)(82310400011)(1800799012)(451199024)(64100799003)(186009)(40470700004)(36840700001)(46966006)(41300700001)(36756003)(5660300002)(40460700003)(2906002)(30864003)(2876002)(82740400003)(426003)(36860700001)(83380400001)(7696005)(966005)(478600001)(47076005)(356005)(8936002)(4326008)(1076003)(8676002)(2616005)(26005)(336012)(86362001)(40480700001)(6916009)(81166007)(316002)(84970400001)(70586007)(70206006)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9822 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B96.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 655cfd1d-ec29-453d-b772-08dbf73aeead X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tmqQcmKd1qyPkCnKRtZtnuycAI8+cd3XIe+ryzWp+fkOl9ZanUTQciQrJIi/DHiyWLFA6OlUWYgVxv8U+3GdF5vECO8fZr72kZpz6B1kj5C1Kpl3RYy5ufjZ4+UY5I3wxfF1jBURJsltpFLa3la+lqvSh0aSZVJKDWKWk8QO+lAgg02ekOi1DyvV7KpI6e/J/vObi6bPePqkPq1K+xuaMhJsZm+9Z8HwryYS8iXb6yzKVnuNOM36rhqf5rSfMCPx04cMoAPaEGBoVAocBB4RVNCzE8qqTKOjysJQ9p5JdM2eOqBibMYpJoQ6WMTL0AWsb3ZtENWwb8s2wZF+eDL7jMG1K0xZSdVhjnAC7yhwOAaJuDLatUDl1SCcjMqu8HuvFr/OQfCijTZ8VkXm4RT3v/EDlykBF3mTZCiv2W3BbkXtGZDQwowTUPF45707fRVDmaQzaiiGeO3i/wbZfusDEdTQFNrqPi9wAGOH1SGPhJMko79Soq39rKUBLZE6iH/UpacoOdyO8LINYRGLGCeQZtcfSu7cM2kKr+MUKKsQnDuf7x/CZ6rO+8dsrR4WliF1hBtVFT5Th+M8Gbh/tND8qtWuAHRoggNK3EFriaPOuEWynfl5UnybYx1lAVM2PeByMj/iJYoclG3JdfCZm5tuNS2K4U4viKW7w5IXAuA37RVTG3PGbl7Y6YAD8l+YCD1hMI1MBRRMcKWtk7mAV1ljWOzgKUlxKd7Lka2+67JG/1QPSxRnKxTC/krdnNsGBMT5VOd9Si/ItQCx8XAWHVHyUg== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(346002)(136003)(396003)(230922051799003)(64100799003)(451199024)(82310400011)(1800799012)(186009)(46966006)(40470700004)(36840700001)(7696005)(83380400001)(426003)(40460700003)(1076003)(2616005)(336012)(26005)(316002)(70206006)(70586007)(6916009)(84970400001)(40480700001)(5660300002)(30864003)(4326008)(2906002)(86362001)(2876002)(8936002)(8676002)(36756003)(41300700001)(966005)(82740400003)(81166007)(478600001)(36860700001)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2023 15:41:20.0201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c9a05cf-a0e1-4ea6-222b-08dbf73af564 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B96.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7738 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for the arm port. This patch adds the _x3 variants of the vld1 intrinsic. The previous vld1_x3 has been updated to vld1q_x3 to take into account that it works with 4-word-length types. vld1_x3 is now only for 2-word-length types. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New. (vld1_f16_x3, vld1_f32_x3): New. (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New. (vld1_bf16_x3): New. (vld1q_types_x3): Updated to use vld1q_x3 from arm_neon_builtins.def * config/arm/arm_neon_builtins.def (vld1_x3): Updated entries. (vld1q_x3): New entries, but comes from the old vld1_x2 * config/arm/neon.md (neon_vld1q_x3): Updated from neon_vld1_x3. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 156 ++++++++++++++++-- gcc/config/arm/arm_neon_builtins.def | 3 +- gcc/config/arm/neon.md | 10 ++ .../gcc.target/arm/simd/vld1_base_xN_1.c | 63 ++++++- .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 7 +- .../gcc.target/arm/simd/vld1_p64_xN_1.c | 7 +- 7 files changed, 231 insertions(+), 22 deletions(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 669b8fffb40..dbc37cafe28 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10316,6 +10316,15 @@ vld1_p64_x2 (const poly64_t * __a) return __rv.__i; } +__extension__ extern __inline poly64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p64_x3 (const poly64_t * __a) +{ + union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10381,6 +10390,42 @@ vld1_s64_x2 (const int64_t * __a) return __rv.__i; } +__extension__ extern __inline int8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s8_x3 (const int8_t * __a) +{ + union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s16_x3 (const int16_t * __a) +{ + union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s32_x3 (const int32_t * __a) +{ + union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s64_x3 (const int64_t * __a) +{ + union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10417,6 +10462,26 @@ vld1_f32_x2 (const float32_t * __a) return __rv.__i; } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f16_x3 (const float16_t * __a) +{ + union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f32_x3 (const float32_t * __a) +{ + union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_u8 (const uint8_t * __a) @@ -10481,6 +10546,42 @@ vld1_u64_x2 (const uint64_t * __a) return __rv.__i; } +__extension__ extern __inline uint8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u8_x3 (const uint8_t * __a) +{ + union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u16_x3 (const uint16_t * __a) +{ + union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x2x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u32_x3 (const uint32_t * __a) +{ + union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x1x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u64_x3 (const uint64_t * __a) +{ + union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_p8 (const poly8_t * __a) @@ -10513,6 +10614,24 @@ vld1_p16_x2 (const poly16_t * __a) return __rv.__i; } +__extension__ extern __inline poly8x8x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p8_x3 (const poly8_t * __a) +{ + union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p16_x3 (const poly16_t * __a) +{ + union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline poly64x2_t @@ -10536,7 +10655,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p64_x3 (const poly64_t * __a) { union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10619,7 +10738,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s8_x3 (const uint8_t * __a) { union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10628,7 +10747,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s16_x3 (const uint16_t * __a) { union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10637,7 +10756,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s32_x3 (const int32_t * __a) { union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10646,7 +10765,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s64_x3 (const int64_t * __a) { union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10728,7 +10847,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f16_x3 (const float16_t * __a) { union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hf (__a); + __rv.__o = __builtin_neon_vld1q_x3v8hf (__a); return __rv.__i; } #endif @@ -10738,7 +10857,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f32_x3 (const float32_t * __a) { union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4sf ((const __builtin_neon_sf *) __a); return __rv.__i; } @@ -10831,7 +10950,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8_x3 (const uint8_t * __a) { union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10840,7 +10959,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u16_x3 (const uint16_t * __a) { union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10849,7 +10968,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u32_x3 (const uint32_t * __a) { union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10858,7 +10977,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u64_x3 (const uint64_t * __a) { union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10935,7 +11054,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8_x3 (const poly8_t * __a) { union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10944,7 +11063,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p16_x3 (const poly16_t * __a) { union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -20944,6 +21063,15 @@ vld1_bf16_x2 (const bfloat16_t * __ptr) return __rv.__i; } +__extension__ extern __inline bfloat16x4x3_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_bf16_x3 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv; + __rv.__o = __builtin_neon_vld1_x3v4bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16 (const bfloat16_t * __ptr) @@ -20965,7 +21093,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16_x3 (const bfloat16_t * __ptr) { union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr); + __rv.__o = __builtin_neon_vld1q_x3v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 07750c03c08..c74f0db645b 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -303,7 +303,8 @@ VAR13 (LOAD1, vld1, v4bf, v8bf) VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) -VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (LOAD1, vld1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR12 (LOAD1LANE, vld1_lane, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 75add42777d..e67cbc247d9 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4968,6 +4968,16 @@ if (BYTES_BIG_ENDIAN) ) (define_insn "neon_vld1_x3" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1))] + "TARGET_NEON" + "vld1.\t%h0, %A1" + [(set_attr "type" "neon_load1_3reg")] +) + +(define_insn "neon_vld1q_x3" [(set (match_operand:CI 0 "s_register_operand" "=w") (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c index 6b0e78d94d7..95314bbe0de 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c @@ -60,7 +60,62 @@ poly16x4x2_t test_vld1_p16_x2 (poly16_t * a) return vld1_p16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file +uint8x8x3_t test_vld1_u8_x3 (uint8_t * a) +{ + return vld1_u8_x3 (a); +} + +uint16x4x3_t test_vld1_u16_x3 (uint16_t * a) +{ + return vld1_u16_x3 (a); +} + +uint32x2x3_t test_vld1_u32_x3 (uint32_t * a) +{ + return vld1_u32_x3 (a); +} + +uint64x1x3_t test_vld1_u64_x3 (uint64_t * a) +{ + return vld1_u64_x3 (a); +} + +int8x8x3_t test_vld1_s8_x3 (int8_t * a) +{ + return vld1_s8_x3 (a); +} + +int16x4x3_t test_vld1_s16_x3 (int16_t * a) +{ + return vld1_s16_x3 (a); +} + +int32x2x3_t test_vld1_s32_x3 (int32_t * a) +{ + return vld1_s32_x3 (a); +} + +int64x1x3_t test_vld1_s64_x3 (int64_t * a) +{ + return vld1_s64_x3 (a); +} + +float32x2x3_t test_vld1_f32_x3 (float32_t * a) +{ + return vld1_f32_x3 (a); +} + +poly8x8x3_t test_vld1_p8_x3 (poly8_t * a) +{ + return vld1_p8_x3 (a); +} + +poly16x4x3_t test_vld1_p16_x3 (poly16_t * a) +{ + return vld1_p16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c index 3ec7a5e1986..c1935da0a4c 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c @@ -10,4 +10,9 @@ bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a) return vld1_bf16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ \ No newline at end of file +bfloat16x4x3_t test_vld1_bf16_x3 (bfloat16_t * a) +{ + return vld1_bf16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c index c0e5ea49142..20363239f5b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c @@ -10,4 +10,9 @@ float16x4x2_t test_vld1_f16_x2 (float16_t * a) return vld1_f16_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +float16x4x3_t test_vld1_f16_x3 (float16_t * a) +{ + return vld1_f16_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c index 3ccea520ddc..210de511c71 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c @@ -10,4 +10,9 @@ poly64x1x2_t test_vld1_p64_x2 (poly64_t * a) return vld1_p64_x2 (a); } -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ +poly64x1x3_t test_vld1_p64_x3 (poly64_t * a) +{ + return vld1_p64_x3 (a); +} + +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ -- 2.25.1