From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id 229693858298 for ; Tue, 12 Dec 2023 19:33:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 229693858298 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 229693858298 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::332 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702409599; cv=none; b=XlKAKOLGNb6w8MnTEV7w/skVqosA15MwitWDP0MTrV69mqYQk3EnLUq5OFByjNBJ11IKp64fQVpy3DdoqtMo3C72UtsYEfoQk4u7ge5n9FoqQteMpeR9RsgLbyH4fWc1MRxA2pF7MaOwqFm4q05PySNCXCuYZbioy6OdT3zI23A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702409599; c=relaxed/simple; bh=c4g4L1HVhcEx4voUgNdEp7OXmXsxQctK1+PTGIAwy0I=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=YIV0hKbFQw2F5qtR3vv6SWBi3uSg63NpfyYlTTcOr+TBOQOtMzGQtqt5i5rJVafYIqcROvPepaAWDvLS8BHq8y5LZ6qgx8T0tLNsDvCvgrIOUtg0HFtVct+smM/SO6yaJ8OmQNyLIwL3K6vxj46Z/a3hSSxa9CxjTkk/u5U2sjw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40c25973988so62956535e9.2 for ; Tue, 12 Dec 2023 11:33:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1702409596; x=1703014396; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=BUD9v0bq9DTyOdSsA7QGp7788QGsNFlflxHHGa6g75uLfbhL3zXdrHGuPqtOa44DSi XSSSWTGNlXYcxsUEQ/R4elBSH4+94ImQY4NmELQsn7EdGeO+cDBIVg0NP0kq7yEiLbnr UDioxYt3QXIHWHJuCUNduK9tYMUJRVU9W26GoAJ/CXwqIYagNaPzsvcS+I3iTKCY1wlW TNY3bg+8h6b4MsPNbtGhgf0dTs33bR+vJsv9OHmWTx9NfK/JdOVCPl0h5y581mH1jOpS 4jUxUMkI7/2MSyNmIkoNWjFUHxvo4BeyIRWdMImXaHbfv42SUfuS/qmFySefPhif+CUd okRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702409596; x=1703014396; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=EG7d5buXx9J2OUeXnFCxVd8qHz7MYNGIdypGYi8yJ+s9vzpKR6bdYveo1oMzGkeJEH NxrmT+uU3tpAuKfeeluFRaaSIE+07GLGMhuny5qe0odjTjpvbKsRK7H4o1sw5tnD3qMy L9NxXxguP098m9sN1r6XPae7lQ5O4An4L5M96aosstiEyqZiLdhKrd09Cyw08jfjo0mL ybtMTrK7lElXSN5Bt4QrMWaWIz7vDFpTvmHajpd6BWjHtAsf/8QX2yjWPINaLH/dYI66 eZaJKkCpvx2wB60a2SDFCk8F4M7qcwoSHpCB4xtb+hR12lJp4Z+eorjrJiyujxGNOCp+ 9ipw== X-Gm-Message-State: AOJu0Ywn6jL+Rf6ojZJtdB86iyE2GJwXr+z1JOfwA3sOToM73tpSj5nM xlaE3WDemQDICL4nAC5KgV2sLqsqICsmkzqgpko= X-Google-Smtp-Source: AGHT+IFIHyWJefFxSAuOowYr+V9YSzna+Zgp6h9UHKdwf37LjyCsxemFWZH4lQK7DQgqKbYRXHvaWA== X-Received: by 2002:a05:600c:30d2:b0:40c:4378:f117 with SMTP id h18-20020a05600c30d200b0040c4378f117mr2649753wmn.76.1702409596021; Tue, 12 Dec 2023 11:33:16 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm19934150wmb.27.2023.12.12.11.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 11:33:15 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Tue, 12 Dec 2023 19:32:52 +0000 Message-Id: <20231212193253.220195-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231212193253.220195-1-mary.bennett@embecosm.com> References: <20231128131615.3986922-1-mary.bennett@embecosm.com> <20231212193253.220195-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index c7a2ba07bcc..92bf0b5d6a6 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" -- 2.34.1