From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id EB4E93861869 for ; Fri, 15 Dec 2023 08:06:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB4E93861869 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EB4E93861869 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.92 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702627585; cv=none; b=sBN+7HNmIzSZukeVYF9zjLaS2OlQ1zW6tbdwCnT2ELNH/z9PjMrJqy4wlvaZwiSotCEDKTRIDhGJeCatJLRzAbK2oK8z8WUyTiig/cD6pFqn1CDQ6I77GYoTSpeHKmw/X4YCv5Idr2C4WfmRWEWxovrH7VMs1OyKmgFrURENUBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702627585; c=relaxed/simple; bh=RZvrOgmNEExs3DW6+2Q2a6abmqMtmhw72zpiOsjxNjU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JW3CTdIX2guOo4yXFsC0+mLSSUykYAUsM3AavGyCFnvQN7b5loPyac731GYiMigQybq7RreZlrPeabyBcTmY8Vw0Jgvy3xF2pfxSG+rwkn9ugjTxzt7OumKLqPnhDM4KjutXA1HwG6HT9rZX/tt4BM6bqzd2uEFcbx5LvXx7jOk= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp90t1702627574tsgrid0w Received: from server1.localdomain ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 15 Dec 2023 16:06:13 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJn90g5c68u3H1sb2uAIp8nZ83TxB8I5GSG2pA16UpCrxvmOjZSIx LEY72yyp06tPiIhRlNEPH2SaRnwF2Rh9fhgc1Zv/fvDYyxElvNoqi++9V1Ma8QAUHkSaVNB nQB1zMfWjqXVNPs5VaUw1gDtdEbU4ojfCzM+tSWlFzS0HiCRBNASq/708ElVy6P8ZM0zRkp Qbe335vFXgqULLcYNbGU6bOtY/Lfg/1/tGrwOGImzhYZacmagfhZmYsCknBt1XLEXYtww+r hJ+d7pm/B0uu1M9JJOPYyZelXvun0lCYkPATmfoo5x73J5D5nWibj2v9Qyzj8135wJA0si7 8arZaJCjHgaRwTFQg1n5X6KrkCsNoIOQb8Hqxw2jD2KufWfhwdVndNXEji/FRk8eArszLAJ dY9N4J+63TU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13338630512327065850 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Remove xfail for some of the SLP tests Date: Fri, 15 Dec 2023 16:06:10 +0800 Message-Id: <20231215080610.92416-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Due to recent middle-end cost model changes, now we can do more VLA SLP. Fix these following regressions: XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvid\\.v XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvid\\.v XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-assembler \\tvid\\.v XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-assembler \\tvid\\.v XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-16.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-3.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-3.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-5.c scan-tree-dump-times optimized ".VEC_PERM" 1 XPASS: gcc.target/riscv/rvv/autovec/partial/slp-5.c scan-tree-dump-times optimized ".VEC_PERM" 1 Committed. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Remove xfail of M2. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto. --- .../gcc.target/riscv/rvv/autovec/partial/slp-1.c | 8 ++++---- .../gcc.target/riscv/rvv/autovec/partial/slp-16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/partial/slp-3.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/partial/slp-5.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c index 34622ce9aff..948b20b68d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c @@ -20,7 +20,7 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen - instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ -/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ +/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c index 80c77ef679a..7b23cafab3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c @@ -20,7 +20,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n) } /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen - instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ -/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */ + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */ +/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1"} } } } */ /* { dg-final { scan-assembler-not {\tvmul} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c index 75298bd7525..3622c59c439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c @@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen - instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c index c1b31a430f2..5c0a6775474 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c @@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n) } /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen - instead of SLP when riscv-autovec-lmul=m1 or m2. */ -/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" "--param riscv-autovec-lmul=m8" } } } } */ + instead of SLP when riscv-autovec-lmul=m1. */ +/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m8" } } } } */ -- 2.36.1