From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by sourceware.org (Postfix) with ESMTPS id 527FF3858417 for ; Tue, 19 Dec 2023 09:53:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 527FF3858417 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 527FF3858417 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::32c ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702979634; cv=none; b=xAE8UH/9mwq6sqE0mOKe3ha9zB3/Co69QE5lkccajIZ2+gK9L9Qn/ugYBkt6wMMiOIrxbCUG4HwBGOums2H4rVezvN1WPKi6Kh8ZCtvDnmOvk/k/OkGItPeLUfya+o9yrHeorfFNH4CWgF37bE/yUlpkHCawDhWy1BOUjBHojAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702979634; c=relaxed/simple; bh=TP814YteRP+A9SWvtQ8tHZgO3Oj3EbIPN6sNHjHlGCo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=q6WYaU4HsVxaYkyOiqOvkjqz1yR7F91D/EZdRNM5CfjwQ7sqvsbmjJTlEeHKkfTblyfdeR6ZljsZYRE2euysqdzx2puilyKHXg8r1X128jTQNzLJVaVqLjJoihVZBmTfPQN1176K1eeLBlzdMa6Sc5Z7F8NVB1gL3z9JFWQepMI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-40c6ea99429so43259865e9.3 for ; Tue, 19 Dec 2023 01:53:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1702979630; x=1703584430; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=3zjNc9LtT4nYN3hz8B45DkHwaP5PhZLK511o9y8w54w=; b=tA/Y9y+p/zKD6LieAVaWtzEKMfGx85sTicyYznGNWVM6LNbz1loYBltLvra2qBL2GD fn10zrgSuQbg/k2P7x3r6Ej6wIJJ8bhTjoJ3jOKQBSHTczv+MYE+dTUOnFclCqg8NIZG R9eHmxX9EJ+WlR+8wmruGZY5AncBMUfuop49g7hwZsfridxaE+p161ZgnAQXlfLazTUK FRQSm4QHZttIH6wYJtqQlzsEBqI45gIj99lxM26b4AHAX8RfVZSdopPF3fUDJDLzveVi apn6DmQ3ZceK7+H/mm72MsGGaWnjqjEICczyQJUCKSCDsXpGS3c/M/l4eqrSr1vUC6Mb We9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702979630; x=1703584430; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3zjNc9LtT4nYN3hz8B45DkHwaP5PhZLK511o9y8w54w=; b=omNzS173+ssNjZu1ziOJu2tUx1Gs8fA6eF/N3HgXFBoFKtLJpnMunKyi0x9IKk0/XN VaqBGsNz1bQauTJcNmBtf7Gp0TQHI/LNfo1iGroLK8DoWLQ23/s07jmbxomUUxE/BDMr 7qANbWB39BihP6kxe7/l3Lhkk+vX4c0YwctgjqW/rdZpLJ3kOd5H0ojynek6YjS6HCiT FedV6abPWdxvx3RTKo/NWbXnp+qvs2tNN827JP6kok5urtPbgeJQt7mXEtWG3VykOyNd 6cX6F5qCBCt7JIFigiYFPhcsWQ40ZqEXal6dKmB+DmZV3bKlZr1S4I8p60qdZbPlg5LM qOEA== X-Gm-Message-State: AOJu0YxTnTW9h+EDcuMNxP/E2txNaMKjW9tvIMtgjLpkjTFPQH9luJ7W 6Az0W+yUuzSBzx6DGIU4uFKE08zAtqe/3+B0yTZ/Mw== X-Google-Smtp-Source: AGHT+IFvaNofB4Vbt6sUSeRq84vDdfNxAHIl815SvoJBa0qxqUB47O4CN7IAiw48RpwZB3cxxLCx0A== X-Received: by 2002:a05:600c:c17:b0:402:ee71:29 with SMTP id fm23-20020a05600c0c1700b00402ee710029mr6447130wmb.10.1702979629622; Tue, 19 Dec 2023 01:53:49 -0800 (PST) Received: from slewis-laptop.ba.rivosinc.com ([51.52.155.69]) by smtp.gmail.com with ESMTPSA id q19-20020a05600c46d300b0040b632f31d2sm2079985wmo.5.2023.12.19.01.53.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 01:53:49 -0800 (PST) From: Sergei Lewis To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 0/3] RISC-V: vectorised memory operations Date: Tue, 19 Dec 2023 09:53:45 +0000 Message-Id: <20231219095348.356551-1-slewis@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patchset permits generation of inlined vectorised code for movmem, setmem and cmpmem, if and only if the operation size is at least one and at most eight vector registers' worth of data. Further vectorisation rapidly becomes debatable due to code size concerns; however, for these simple cases we do have an unambiguous performance win without sacrificing too much code size compared to a libc call. Changes in v2: * run clang-format over the code in addition to the contrib/check_GNU_style.sh that was used for v1 * remove string.h include and refer to __builtin_* memory functions in multilib tests * respect stringop_strategy (don't vectorise if it doesn't include VECTOR) * use an integer constraint for movmem length parameter * use TARGET_MAX_LMUL unless riscv-autovec-lmul=dynamic to ensure we respect the user's wishes if they request specific lmul * add new unit tests to check that riscv-autovec-lmul is respected * PR target/112109 added to changelog for patch 1/3 as requested Sergei Lewis (3): RISC-V: movmem for RISCV with V extension RISC-V: setmem for RISCV with V extension RISC-V: cmpmem for RISCV with V extension gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-string.cc | 190 ++++++++++++++++++ gcc/config/riscv/riscv.md | 51 +++++ .../gcc.target/riscv/rvv/base/cmpmem-1.c | 88 ++++++++ .../gcc.target/riscv/rvv/base/cmpmem-2.c | 74 +++++++ .../gcc.target/riscv/rvv/base/cmpmem-3.c | 45 +++++ .../gcc.target/riscv/rvv/base/cmpmem-4.c | 62 ++++++ .../gcc.target/riscv/rvv/base/movmem-1.c | 60 ++++++ .../gcc.target/riscv/rvv/base/setmem-1.c | 103 ++++++++++ .../gcc.target/riscv/rvv/base/setmem-2.c | 51 +++++ .../gcc.target/riscv/rvv/base/setmem-3.c | 69 +++++++ 11 files changed, 795 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c -- 2.34.1