From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 712FA385E019 for ; Wed, 20 Dec 2023 06:56:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 712FA385E019 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 712FA385E019 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703055373; cv=none; b=Pqco/o6OB8rp1GlbNOuv9ct9crEP0OFu6bZwYTZXjcGeNPo4UqIVUmWwePJdGOu7pLPCCW93xfyiF87AAqT60iWf4nzTvtmtv1bm/3eMzIjKS0IJW9yAVBI1dalR7TZf9FIIp7x6ZdzFFs0lxkoKW3hiuvr/EMNmWehyP9yLayw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703055373; c=relaxed/simple; bh=ATQ4sshbxj2HG9/tzpK+PUXiTsvSNPnHiQCoiioaY7Q=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=fOyK8+/cViMCrvWrXqWVjmlgg+qi7W91n1QYTIKf1GaN4AO7ZSNHsbjHVG9Fu8X2UGp9zp9QXKLoac88WemBfFaqWWfgmsXuXEbKirprDxg9yx9eTw8GBGG+cQHvkGTuM4T6hrKd2GLSsH2YHCN0PZRR1+se0ZB9Zfn8NkKAnow= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703055372; x=1734591372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ATQ4sshbxj2HG9/tzpK+PUXiTsvSNPnHiQCoiioaY7Q=; b=Qh41hgO58MAcERI73g6CtvXY4H2d52na826ekn7q5XJxf7jOSJJ7zfym qrzCSkfUxgqz0fVHYFCMPgi7Q80xHyH6S3TR4nCuPPPwPHDkILw2/nnPc UCAqKiE3IvYJLJbQSN+KQpYuXA5lVjqB7XSCFUqO7ufDYwova16kaGkPO M8M/g8Yak5tNIhHJryTntg0gzwvILfCRTb9hycpAwdtX0vaMB42agdEHr CU52hpGpi7HsoQnaAe/V0q7Qnvp2gBKoMIDbN7hbRDbipNxmIH3PTouLP qqEEciKaZpA3Gl9NfONhb6r8tXBMDDdftScWR1s68UDIWWqChQFDSivVh w==; X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="3008031" X-IronPort-AV: E=Sophos;i="6.04,290,1695711600"; d="scan'208";a="3008031" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2023 22:56:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="776238176" X-IronPort-AV: E=Sophos;i="6.04,290,1695711600"; d="scan'208";a="776238176" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga002.jf.intel.com with ESMTP; 19 Dec 2023 22:56:08 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 6E96010057E2; Wed, 20 Dec 2023 14:56:07 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com, jeffreyalaw@gmail.com Subject: [PATCH v2] RISC-V: Bugfix for the const vector in single steps Date: Wed, 20 Dec 2023 14:56:06 +0800 Message-Id: <20231220065606.2695737-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231220023922.1076198-1-pan2.li@intel.com> References: <20231220023922.1076198-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to fix the below execution failure. FAIL: gcc.dg/vect/pr92420.c -flto -ffat-lto-objects execution test The will be one single step const vector like { -4, 4, -3, 5, -2, 6, -1, 7, ...}. For such const vector generation with single step, we will generate vid + diff here. For example as below, given npatterns = 4. v1= {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8... } v2 (diff) = {3 - 0, 2 - 1, 1 - 2, 0 - 3, 7 - 4, 6 - 5, 5 - 6, 4 - 7...} = {3, 1, -1, 3, 3, 1, -1, 3 ...} v1 = vd + vid. Unfortunately, that cannot work well for { -4, 4, -3, 5, -2, 6, -1, 7, ...} because it has one implicit requirement for the diff. Aka, the diff sequence in npattern are repeated. For example the v2 (diff) as above. The diff between { -4, 4, -3, 5, -2, 6, -1, 7, ...} and vid are not npattern size repeated and then we have wrong code here. We implement one new code gen the sequence like { -4, 4, -3, 5, -2, 6, -1, 7, ...}. The below tests are passed for this patch. * The RV64 regression test with rv64gcv configuration. * The run test gcc.dg/vect/pr92420.c for below configurations. riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Add restriction for the vid-diff code gen and implement general one. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/bug-7.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 84 +++++++++++++++---- .../gcc.target/riscv/rvv/autovec/bug-7.c | 61 ++++++++++++++ 2 files changed, 130 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 486f5deb296..5a5899e85ae 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1257,24 +1257,78 @@ expand_const_vector (rtx target, rtx src) else { /* Generate the variable-length vector following this rule: - { a, b, a, b, a + step, b + step, a + step*2, b + step*2, ...} - E.g. { 3, 2, 1, 0, 7, 6, 5, 4, ... } */ - /* Step 2: Generate diff = TARGET - VID: - { 3-0, 2-1, 1-2, 0-3, 7-4, 6-5, 5-6, 4-7, ... }*/ + { a, b, a + step, b + step, a + step*2, b + step*2, ... } */ rvv_builder v (builder.mode (), builder.npatterns (), 1); - for (unsigned int i = 0; i < v.npatterns (); ++i) + bool diff_seq_repeated_p = true; + + for (unsigned i = 0; i < v.npatterns (); i++) + { + poly_int64 diff_0 = rtx_to_poly_int64 (builder.elt (i)) - i; + poly_int64 diff_1 = rtx_to_poly_int64 ( + builder.elt (v.npatterns () + i)) - v.npatterns () - i; + + if (maybe_ne (diff_0, diff_1)) + { + diff_seq_repeated_p = false; + break; + } + } + + if (diff_seq_repeated_p) + { + /* Case 1: For example as below: + {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8... } + We have 3 - 0 = 3 equals 7 - 4 = 3, the sequence is + repeated as below after minus vid. + {3, 1, -1, -3, 3, 1, -1, -3...} + Then we can simplify the diff code gen to at most + npatterns(). */ + + /* Step 1: Generate diff = TARGET - VID. */ + for (unsigned int i = 0; i < v.npatterns (); ++i) + { + poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; + v.quick_push (gen_int_mode (diff, v.inner_mode ())); + } + + /* Step 2: Generate result = VID + diff. */ + rtx vec = v.build (); + rtx add_ops[] = {target, vid, vec}; + emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), + BINARY_OP, add_ops); + } + else { - /* Calculate the diff between the target sequence and - vid sequence. The elt (i) can be either const_int or - const_poly_int. */ - poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; - v.quick_push (gen_int_mode (diff, v.inner_mode ())); + /* Case 2: For example as below: + { -4, 4, -4 + 1, 4 + 1, -4 + 2, 4 + 2, -4 + 3, 4 + 3, ... } + */ + + /* Step 1: Generate { a, b, a, b, ... } */ + for (unsigned int i = 0; i < v.npatterns (); ++i) + v.quick_push (builder.elt (i)); + rtx new_base = v.build (); + + /* Step 2: Generate tmp = VID >> LOG2 (NPATTERNS).  */ + rtx shift_count + = gen_int_mode (exact_log2 (builder.npatterns ()), + builder.inner_mode ()); + rtx tmp = expand_simple_binop (builder.mode (), LSHIFTRT, + vid, shift_count, NULL_RTX, + false, OPTAB_DIRECT); + + /* Step 3: Generate tmp2 = tmp * step.  */ + rtx tmp2 = gen_reg_rtx (builder.mode ()); + rtx step + = simplify_binary_operation (MINUS, builder.inner_mode (), + builder.elt (v.npatterns()), + builder.elt (0)); + expand_vec_series (tmp2, const0_rtx, step, tmp); + + /* Step 4: Generate target = tmp2 + new_base.  */ + rtx add_ops[] = {target, tmp2, new_base}; + emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), + BINARY_OP, add_ops); } - /* Step 2: Generate result = VID + diff. */ - rtx vec = v.build (); - rtx add_ops[] = {target, vid, vec}; - emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), - BINARY_OP, add_ops); } } else if (builder.interleaved_stepped_npatterns_p ()) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c new file mode 100644 index 00000000000..9acac391f65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c @@ -0,0 +1,61 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#define N 4 +struct C { int l, r; }; +struct C a[N], b[N], c[N]; +struct C a1[N], b1[N], c1[N]; + +void __attribute__((noinline)) +init_data_vec (struct C * __restrict a, struct C * __restrict b, + struct C * __restrict c) +{ + int i; + + for (i = 0; i < N; ++i) + { + a[i].l = N - i; + a[i].r = i - N; + + b[i].l = i - N; + b[i].r = i + N; + + c[i].l = -1 - i; + c[i].r = 2 * N - 1 - i; + } +} + +int +main () +{ + int i; + + init_data_vec (a, b, c); + +#pragma GCC novector + for (i = 0; i < N; ++i) + { + a1[i].l = N - i; + a1[i].r = i - N; + + b1[i].l = i - N; + b1[i].r = i + N; + + c1[i].l = -1 - i; + c1[i].r = 2 * N - 1 - i; + } + + for (i = 0; i < N; i++) + { + if (a[i].l != a1[i].l || a[i].r != a1[i].r) + __builtin_abort (); + + if (b[i].l != b1[i].l || b[i].r != b1[i].r) + __builtin_abort (); + + if (c[i].l != c1[i].l || c[i].r != c1[i].r) + __builtin_abort (); + } + + return 0; +} -- 2.34.1