From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) by sourceware.org (Postfix) with ESMTPS id D732F3858C2C for ; Wed, 20 Dec 2023 12:27:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D732F3858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D732F3858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703075277; cv=none; b=KngrSmkQliyRQdJS7171VlsGFqdSrgfBS8JF6hEZpwV9znm2RgPKiN1XYi06d+r3gbK/inkwIALSXo5DYgJBq6OaSsaPdBRLeDal2PRa6u3J8ejAG3l5FSNYJzCDj8rKjDDlW3r+mm5L8FPV4T/Z3BPqU0MxxhU+mlEIEO/rDsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703075277; c=relaxed/simple; bh=yhjIjLE2y2xqLINg/Tw4kHDKeC4Vb34o7mUnJ7cQ/Nc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=mR2Ci9+KEDeLD2ITuu0TGG4pdDgijJjkE4ZVbIklPzpzO1enag/k7T0T4khusIr86f6GWkzA/mTrF+zDzQk+Su4HgAI85IWDWVJ8GL6m5Z3YGZOIG83/5e+wPHIMAF3U3afu5sGCKbaZIpY1dVTeH3H9B9dxzNoRQjbMj+4pdjY= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R141e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=cooper.joshua@linux.alibaba.com;NM=1;PH=DS;RN=11;SR=0;TI=SMTPD_---0VyuUSNY_1703075265; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VyuUSNY_1703075265) by smtp.aliyun-inc.com; Wed, 20 Dec 2023 20:27:50 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns. Date: Wed, 20 Dec 2023 20:27:32 +0800 Message-Id: <20231220122732.449-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231220122055.343-1-cooper.joshua@linux.alibaba.com> References: <20231220122055.343-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-17.8 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in files like riscv.md. gcc/ChangeLog: * config/riscv/predicates.md (vector_csr_operand): Define vector_csr_opeand for vector. * config/riscv/vector.md: Use newly defined csr_operand for vector. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config/riscv/predicates.md | 4 ++++ gcc/config/riscv/vector.md | 8 ++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 6bf6e186641..1a3a4f1ecbb 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -63,6 +63,10 @@ (define_predicate "csr_operand" (ior (match_operand 0 "const_csr_operand") (match_operand 0 "register_operand"))) +(define_predicate "vector_csr_operand" + (ior (match_operand 0 "const_csr_operand") + (match_operand 0 "register_operand"))) + ;; V has 32-bit unsigned immediates. This happens to be the same constraint as ;; the csr_operand, but it's not CSR related. (define_predicate "vector_scalar_shift_operand" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f607d768b26..036b2425f32 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1496,7 +1496,7 @@ (define_insn_and_split "*vec_duplicate" (define_insn "@vsetvl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1542,7 +1542,7 @@ (define_insn "vsetvl_vtype_change_only" ;; in vsetvl instruction pattern. (define_insn "@vsetvl_discard_result" [(set (reg:SI VL_REGNUM) - (unspec:SI [(match_operand:P 0 "csr_operand" "rK") + (unspec:SI [(match_operand:P 0 "vector_csr_operand" "rK") (match_operand 1 "const_int_operand" "i") (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL)) (set (reg:SI VTYPE_REGNUM) @@ -1564,7 +1564,7 @@ (define_insn "@vsetvl_discard_result" ;; such pattern can allow us gain benefits of these optimizations. (define_insn_and_split "@vsetvl_no_side_effects" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1608,7 +1608,7 @@ (define_insn_and_split "*vsetvldi_no_side_effects_si_extend" [(set (match_operand:DI 0 "register_operand") (sign_extend:DI (subreg:SI - (unspec:DI [(match_operand:P 1 "csr_operand") + (unspec:DI [(match_operand:P 1 "vector_csr_operand") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand") (match_operand 4 "const_int_operand") -- 2.17.1