[PATCH] RISC-V: Add --with-cmodel configure-time argument

[Palmer Dabbelt <palmer@rivosinc.com>]

I couldn't find another way to set the default code model.

gcc/ChangeLog:

	* config.gcc (RISC-V): Add --with-cmodel
	* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Use
	TARGET_RISCV_DEFAULT_CMODEL
---
I thought we had this already, but I figured I'd double-check my "ya,
that's easy we'll just add a --with-cmodel=large test to the CI" reply.
So maybe there's another way to do this, it's also entirely untested...
---
 gcc/config.gcc           | 15 +++++++++++++--
 gcc/config/riscv/riscv.h |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..9162e793b7d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4659,7 +4659,7 @@ case "${target}" in
 		;;
 
 	riscv*-*-*)
-		supported_defaults="abi arch tune riscv_attribute isa_spec"
+		supported_defaults="abi arch tune riscv_attribute isa_spec cmodel"
 
 		case "${target}" in
 		riscv-* | riscv32*) xlen=32 ;;
@@ -4700,6 +4700,17 @@ case "${target}" in
 			;;
 		esac
 
+		case "${with_cmodel}" in
+		""|default|"medlow")
+			with_cmodel="CM_MEDLOW"
+			;;
+		"medany")
+			with_cmodel="CM_MEDANY"
+			;;
+		"large")
+			with_cmodel="CM_LARGE"
+			;;
+		esac
 
 		# Infer arch from --with-arch, --target, and --with-abi.
 		case "${with_arch}" in
@@ -4725,7 +4736,7 @@ case "${target}" in
 		if test "x${PYTHON}" != x; then
 			with_arch=`${PYTHON} ${srcdir}/config/riscv/arch-canonicalize -misa-spec=${with_isa_spec} ${with_arch}`
 		fi
-		tm_defines="${tm_defines} TARGET_RISCV_DEFAULT_ARCH=${with_arch}"
+		tm_defines="${tm_defines} TARGET_RISCV_DEFAULT_ARCH=${with_arch} TARGET+RISCV_DEFAULT_CMODEL=${with_cmodel}"
 
 		# Make sure --with-abi is valid.  If it was not specified,
 		# pick a default based on the ISA, preferring soft-float
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..2d69b5276ef 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -112,7 +112,7 @@ ASM_MISA_SPEC
 "%{march=*:%:riscv_expand_arch(%*)} "				\
 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 
-#define TARGET_DEFAULT_CMODEL CM_MEDLOW
+#define TARGET_DEFAULT_CMODEL TARGET_RISCV_DEFAULT_CMODEL
 
 #define LOCAL_LABEL_PREFIX	"."
 #define USER_LABEL_PREFIX	""
-- 
2.43.0