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From: Edwin Lu <ewlu@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, kito.cheng@gmail.com
Subject: Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines
Date: Wed, 20 Dec 2023 14:11:57 -0800	[thread overview]
Message-ID: <9a30c4b3-3b78-41f4-8e72-994275d68e26@rivosinc.com> (raw)
Message-ID: <20231220221157.uEF5euC2NSUHEEH3Dr2lMQwlYX60Nitu2BZlLwULmpI@z> (raw)
In-Reply-To: <819cc2ca-38ef-49dc-9d1e-e5af60ccd66b@gmail.com>

On 12/20/2023 10:50 AM, Jeff Law wrote:
> 
> 
> On 12/15/23 11:53, Edwin Lu wrote:
>> This patch does not create vector related insn reservations for
>> generic.md and sifive-7.md. It updates/creates insn reservations
>> for all non-vector typed insns
>>
>> gcc/ChangeLog:
>>
>>     * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update 
>> reservation
>>     (generic_ooo_branch): ditto
>>     * config/riscv/generic.md (generic_sfb_alu): ditto
>>     * config/riscv/sifive-7.md (sifive_7_popcount): ditto
>>
>> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
>> ---
>>   gcc/config/riscv/generic-ooo.md | 16 +++++++++++++---
>>   gcc/config/riscv/generic.md     | 13 +++++++++----
>>   gcc/config/riscv/sifive-7.md    | 12 +++++++++---
>>   3 files changed, 31 insertions(+), 10 deletions(-)
>>
>> diff --git a/gcc/config/riscv/generic-ooo.md 
>> b/gcc/config/riscv/generic-ooo.md
>> index 78b9e48f935..de93245f965 100644
>> --- a/gcc/config/riscv/generic-ooo.md
>> +++ b/gcc/config/riscv/generic-ooo.md
>> @@ -95,7 +95,7 @@ (define_insn_reservation "generic_ooo_float_store" 6
>>   ;; Vector load/store
>>   (define_insn_reservation "generic_ooo_vec_load" 6
>>     (and (eq_attr "tune" "generic_ooo")
>> -       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
>> +       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,rdfrm"))
>>     "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
> Hmm, I don't think "rdfrm" is really a vector load.  It's really a read 
> of some bits in the fpcsr which elsewhere is handled as type fmove.  I'd 
> actually suggest fixing vector.md to use fmove on the appropriate insn, 
> then dropping rdfrm entirely.
> Sounds good!
> 
> 
>>   (define_insn_reservation "generic_xfer" 3
>>     (and (eq_attr "tune" "generic")
>> -       (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
>> +       (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp,cbo"))
>>     "alu")
> cbo is probably closer to a load/store than it is a transfer operation.
> 
That makes sense. I wasn't sure where exactly to put it since we have 
two separate insn reservations for load and store and from my 
understanding, the same type cannot be in two separate insn 
reservations. Would a new insn reservation like
(define_insn_reservation "generic_load_store" 2 ...) work?

>>   (define_insn_reservation "generic_branch" 1
>>     (and (eq_attr "tune" "generic")
>> -       (eq_attr "type" "branch,jump,call,jalr"))
>> +       (eq_attr "type" "branch,jump,call,jalr,ret,trap,pushpop"))
>> +  "alu")
> pushpop are a mix of some pure memory operations and some mixed memory + 
> branch.
> 
> However, from a scheduling standpoint the branch isn't particularly 
> interesting.  So I'd have pushpop as a load/store.
> 
Same as above

Edwin


  reply	other threads:[~2023-12-20 22:12 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-15 18:53 [PATCH 0/3][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
2023-12-15 18:53 ` [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines Edwin Lu
2023-12-20 18:50   ` Jeff Law
2023-12-20 22:11     ` Edwin Lu [this message]
2023-12-20 22:11       ` Edwin Lu
2023-12-21  6:59       ` Jeff Law
2023-12-15 18:53 ` [PATCH 2/3][RFC] RISC-V: Add vector related reservations Edwin Lu
2023-12-20 18:57   ` Jeff Law
2023-12-20 22:55     ` Edwin Lu
2023-12-20 22:55       ` Edwin Lu
2023-12-26 21:21       ` Edwin Lu
2023-12-15 18:53 ` [PATCH 3/3][RFC] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
2023-12-20 18:57   ` Jeff Law

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