From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id DF9BA385840C for ; Fri, 22 Dec 2023 08:23:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF9BA385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DF9BA385840C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703233423; cv=none; b=UoNuRymy+YJgvU5Gsr/7R6lOBLmfRdvEQ3SUTS1B18idFmwPuXbmekacLW6p+AjSBPnAjyCS+BtKlH8GimwwzHrsX8ShiCz/pf+XWXYWmsOEyP47sCgCGXEtmgnElzHvDNkDoGif2ymlT4pLS0zsNTlqBKyszzpisJVpvGjMxXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703233423; c=relaxed/simple; bh=tMG2/0tejWU9cphBSIRuoPzujhBwbjSuxPBNzBVCOIg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Z812/ktMMQ0OogJSi7mn1uBdMhRC+6dWK5QZAvQFCjVpIbyTLHG3O49RE8E04QMGq9fqP0MjuKoUBbnVLQyNT+AdsSlV4LlYGoUnA1mgimvPt3l+RHzYfyCh4ycRPCKoWURGw09MCDVVPoXRMcba88e0vfB3cZ2sOBFO1BGSMM0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGang-0006RY-Bx for gcc-patches@gcc.gnu.org; Fri, 22 Dec 2023 03:22:38 -0500 Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8Cxueg7R4VlB8wDAA--.19001S3; Fri, 22 Dec 2023 16:22:19 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxD+UzR4VlaVgFAA--.26870S4; Fri, 22 Dec 2023 16:22:18 +0800 (CST) From: Chenghui Pan To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Chenghui Pan Subject: [PATCH v1] LoongArch: Fix insn output of vec_concat templates for LASX. Date: Fri, 22 Dec 2023 16:22:03 +0800 Message-Id: <20231222082203.888077-1-panchenghui@loongson.cn> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8AxD+UzR4VlaVgFAA--.26870S4 X-CM-SenderInfo: psdquxxhqjx33l6o00pqjv00gofq/1tbiAQANBGWE8i4GDQAAs+ X-Coremail-Antispam: 1Uk129KBj93XoWxXrW5Cr18Gr1rKw4kAFyUtwc_yoWrWr4xpr W5uw13Cry5XF4qgayDGayUJw43KFyxGFW7ZFZ8GrZYy3yUW34UK34FkF9aqFyqyr4F9w13 Wa1Ivay8uw4UKrcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jY38nUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=panchenghui@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9,SPF_HELO_NONE=0.001,SPF_PASS=-0.001,T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_FAIL,SPF_HELO_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following instruction block are being generated by vec_concatv32qi (which is generated by vec_initv32qiv16qi) at entrance of foo() function: vldx $vr3,$r5,$r6 vld $vr2,$r5,0 xvpermi.q $xr2,$xr3,0x20 causes the reversion of vec_initv32qiv16qi operation's high and low 128-bit part. According to other target's similar impl and LSX impl for following RTL representation, current definition in lasx.md of "vec_concat" are wrong: (set (op0) (vec_concat (op1) (op2))) For correct behavior, the last argument of xvpermi.q should be 0x02 instead of 0x20. This patch fixes this issue and cleanup the vec_concat template impl. gcc/ChangeLog: * config/loongarch/lasx.md (vec_concatv4di): Delete. (vec_concatv8si): Delete. (vec_concatv16hi): Delete. (vec_concatv32qi): Delete. (vec_concatv4df): Delete. (vec_concatv8sf): Delete. (vec_concat): New template with insn output fixed. --- gcc/config/loongarch/lasx.md | 74 ++++-------------------------------- 1 file changed, 7 insertions(+), 67 deletions(-) diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index eeac8cd984b..a9d948bb606 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -590,77 +590,17 @@ (define_insn "lasx_xvinsgr2vr_" [(set_attr "type" "simd_insert") (set_attr "mode" "")]) -(define_insn "vec_concatv4di" - [(set (match_operand:V4DI 0 "register_operand" "=f") - (vec_concat:V4DI - (match_operand:V2DI 1 "register_operand" "0") - (match_operand:V2DI 2 "register_operand" "f")))] - "ISA_HAS_LASX" -{ - return "xvpermi.q\t%u0,%u2,0x20"; -} - [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DI")]) - -(define_insn "vec_concatv8si" - [(set (match_operand:V8SI 0 "register_operand" "=f") - (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "register_operand" "f")))] - "ISA_HAS_LASX" -{ - return "xvpermi.q\t%u0,%u2,0x20"; -} - [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DI")]) - -(define_insn "vec_concatv16hi" - [(set (match_operand:V16HI 0 "register_operand" "=f") - (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "0") - (match_operand:V8HI 2 "register_operand" "f")))] - "ISA_HAS_LASX" -{ - return "xvpermi.q\t%u0,%u2,0x20"; -} - [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DI")]) - -(define_insn "vec_concatv32qi" - [(set (match_operand:V32QI 0 "register_operand" "=f") - (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "0") - (match_operand:V16QI 2 "register_operand" "f")))] - "ISA_HAS_LASX" -{ - return "xvpermi.q\t%u0,%u2,0x20"; -} - [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DI")]) - -(define_insn "vec_concatv4df" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (vec_concat:V4DF - (match_operand:V2DF 1 "register_operand" "0") - (match_operand:V2DF 2 "register_operand" "f")))] - "ISA_HAS_LASX" -{ - return "xvpermi.q\t%u0,%u2,0x20"; -} - [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DF")]) - -(define_insn "vec_concatv8sf" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "0") - (match_operand:V4SF 2 "register_operand" "f")))] +(define_insn "vec_concat" + [(set (match_operand:LASX 0 "register_operand" "=f") + (vec_concat:LASX + (match_operand: 1 "register_operand" "0") + (match_operand: 2 "register_operand" "f")))] "ISA_HAS_LASX" { - return "xvpermi.q\t%u0,%u2,0x20"; + return "xvpermi.q\t%u0,%u2,0x02"; } [(set_attr "type" "simd_splat") - (set_attr "mode" "V4DI")]) + (set_attr "mode" "")]) ;; xshuf.w (define_insn "lasx_xvperm_" -- 2.39.3