From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) by sourceware.org (Postfix) with ESMTPS id 632A13858D28 for ; Fri, 29 Dec 2023 04:11:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 632A13858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 632A13858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.118 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703823083; cv=none; b=uxQ0uxnTqZ7kjTEqxk5n9ygBMfRd7d+hVVICWU5vEg9XubIwIt+7HMeRZDRnkIqFY90OUo1a094HsG8Y/sdkVVVJ0UnIMreFqRFTE3/xO+cpeh+BXdq+TShWtNdotJPpJJe0nxSHjPRPgbC1Jm4Xy+uE67+yy/Xa8cZcWhjvXmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703823083; c=relaxed/simple; bh=5YjJEl+YUiKSp5MAM9HRIpuhF4kpumr8Eisa43SsMGQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=KeutfylSKFCBYwZ2YK7834v7MMY8ebt2LiQVDAxV0KGAI2kLXaoUoNE1SPme79ZjiqmqkZ+z1GuxrJ+MbWWml8U8utOosfTNRpzPax5BR//QTmpaWB7yvE54c2jICvQnzlEvBZo4fK5X22dnfq3SEfeSbFxs97c38LUIdigBq6I= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R931e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046060;MF=cooper.joshua@linux.alibaba.com;NM=1;PH=DS;RN=11;SR=0;TI=SMTPD_---0VzQHi.O_1703823074; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VzQHi.O_1703823074) by smtp.aliyun-inc.com; Fri, 29 Dec 2023 12:11:17 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns. Date: Fri, 29 Dec 2023 12:10:44 +0800 Message-Id: <20231229041044.1206-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231229040634.1153-1-cooper.joshua@linux.alibaba.com> References: <20231229040634.1153-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch use vector_length_operand instead of csr_operand for vsetvl patterns, so that changes for vector will not affect scalar patterns using csr_operand in riscv.md. gcc/ChangeLog: * config/riscv/vector.md: Use vector_length_operand for vsetvl patterns. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config/riscv/vector.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f607d768b26..b5a9055cdc4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1496,7 +1496,7 @@ (define_insn "@vsetvl" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1542,7 +1542,7 @@ ;; in vsetvl instruction pattern. (define_insn "@vsetvl_discard_result" [(set (reg:SI VL_REGNUM) - (unspec:SI [(match_operand:P 0 "csr_operand" "rK") + (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK") (match_operand 1 "const_int_operand" "i") (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL)) (set (reg:SI VTYPE_REGNUM) @@ -1564,7 +1564,7 @@ ;; such pattern can allow us gain benefits of these optimizations. (define_insn_and_split "@vsetvl_no_side_effects" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1608,7 +1608,7 @@ [(set (match_operand:DI 0 "register_operand") (sign_extend:DI (subreg:SI - (unspec:DI [(match_operand:P 1 "csr_operand") + (unspec:DI [(match_operand:P 1 "vector_length_operand") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand") (match_operand 4 "const_int_operand") -- 2.17.1