From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-119.freemail.mail.aliyun.com (out30-119.freemail.mail.aliyun.com [115.124.30.119]) by sourceware.org (Postfix) with ESMTPS id 0A8583858D28 for ; Fri, 29 Dec 2023 04:14:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0A8583858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0A8583858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.119 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703823254; cv=none; b=URgCJ9F8OkXBub8QiDVdlCj/kK7Rrw90zMNWvEngx32BkMHo7FqfNBR/5M3z+ihsOlyM/DijJDxMgQOsv4yRBIY/h1bn7lWzRx3JSgKxVAkgP35p9hGMW/A9rA0aBvjP5S0kkr5+eOt0aWPAgBL+FgwbfJvwIzox1Zk69a9e4Mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703823254; c=relaxed/simple; bh=J0QwK1L0fkPkOR3BTp6QBE1Df6O7BiCxQ6hHm0hGUBs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=O6yYMzDeu65juo969ZdWU3uLK09lQveD+IIiKnq9rg/WjOIi0CIJzo6PW5hwZnKiJq64cngr3MR8hRv36od1by+h/4wF2ogZfVgSmOUu2Cl0ZhjZOd+4EVjc80gfPEjdGrczVXsecbM3ZXWAaKKZVgjjrd8QsUnPHCzNVA6Uh74= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R101e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045176;MF=cooper.joshua@linux.alibaba.com;NM=1;PH=DS;RN=11;SR=0;TI=SMTPD_---0VzQJsZv_1703823246; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VzQJsZv_1703823246) by smtp.aliyun-inc.com; Fri, 29 Dec 2023 12:14:08 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Date: Fri, 29 Dec 2023 12:13:55 +0800 Message-Id: <20231229041355.1313-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> References: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.0 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extension. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add test marco. * config/riscv/riscv.opt: Add new mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. * gcc.target/riscv/rvv/xtheadvector.c: New test. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 23 +++++++++++++++++++ gcc/config/riscv/riscv-c.cc | 8 +++++-- gcc/config/riscv/riscv.opt | 2 ++ .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++ .../gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++ 5 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index f20d179568d..66b20c154a9 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -368,6 +368,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext () if (lookup ("zcmp")) error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch); } + + if ((lookup ("v") || lookup ("zve32x") + || lookup ("zve64x") || lookup ("zve32f") + || lookup ("zve64f") || lookup ("zve64d") + || lookup ("zvl32b") || lookup ("zvl64b") + || lookup ("zvl128b") || lookup ("zvfh")) + && lookup ("xtheadvector")) + error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector " + "extension or its sub-extensions", m_arch); } /* Parsing function for multi-letter extensions. @@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, + {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR}, + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32}, + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, + {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, + {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, + {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V}, + {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR}, {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index d70eb8ed361..d7c63ead147 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -138,6 +138,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) riscv_ext_version_value (0, 11)); } + if (TARGET_XTHEADVECTOR) + builtin_define_with_int_value ("__riscv_th_v_intrinsic", + riscv_ext_version_value (0, 11)); + /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1); @@ -191,8 +195,8 @@ riscv_pragma_intrinsic (cpp_reader *) { if (!TARGET_VECTOR) { - error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension " - "enabled", + error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or " + "'XTHEADVECTOR' extension enabled", name); return; } diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ede2d655e73..7de5f18e11b 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -449,6 +449,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) Mask(XTHEADSYNC) Var(riscv_xthead_subext) +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) + TargetVariable int riscv_xventana_subext diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c new file mode 100644 index 00000000000..1c764241db6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */ + +int main () { + +#if __riscv_th_v_intrinsic != 11000 +#error "__riscv_th_v_intrinsic" +#endif + + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c new file mode 100644 index 00000000000..d52921e1314 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */ + +#ifndef __riscv_xtheadvector +#error "Feature macro not defined" +#endif + +int +foo (int a) +{ + return a; +} \ No newline at end of file -- 2.17.1