Re: [PATCH] RISC-V: Fix misaligned stack offset for interrupt function

["Fei Gao" <gaofei@eswincomputing.com>]

On 2023-12-25 16:45  Kito Cheng <kito.cheng@sifive.com> wrote:

>+++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
>@@ -0,0 +1,29 @@
>+/* { dg-do compile } */
>+/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */
>+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
>+
>+/*  Make sure no stack offset are misaligned.
>+**  interrupt:
>+**  ...
>+**        sd\tt0,40\(sp\)
>+**        frcsr\tt0
>+**        sw\tt0,32\(sp\)
>+**        sd\tt1,24\(sp\)
>+**        fsd\tft0,8\(sp\)
>+**  ...
>+**        lw\tt0,32\(sp\)
>+**        fscsr\tt0
>+**        ld\tt0,40\(sp\)
>+**        ld\tt1,24\(sp\)
>+**        fld\tft0,8\(sp\)
>+**  ...
>+*/
Hi Kito

The fix is fine but maybe using s0 instead of t0 is better:
1. simpler codes.
2. less stack size

current implementaion:
>+**        sd\tt0,40\(sp\)
>+**        frcsr\tt0
>+**        sw\tt0,32\(sp\)      //save content of frcsr in stack

use s0:
>+**        sd\tt0,40\(sp\)
>+**        frcsr\ts0                //save content of frcsr in s0 instead of stack. If s0 is used as callee saved register, it will be saved again later by legacy codes .

Also adding this change in riscv_expand_prologue & epilogue would be consistent with current stack allocation logic.

I can try it if you think necessary. 

BR
Fei
>+
>+
>+void interrupt(void) __attribute__((interrupt));
>+void interrupt(void)
>+{
>+  asm volatile ("# clobber!":::"t0", "t1", "ft0");
>+}
>+
>+/* { dg-final { check-function-bodies "**" "" } } */
>--
>2.40.1