From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by sourceware.org (Postfix) with ESMTPS id 2D18E3858D33; Fri, 29 Dec 2023 16:18:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2D18E3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2D18E3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703866692; cv=none; b=u4reEgpHDA43tMfXlIvLgnunRHkKP6Ih/43/4ty/cLQn+rDPrmrHOyeoRoZiN7bLiw3iWt9CceF3GvnyerdVd9BaI2F40zECOS+T4YTZgkVs8k/poS0tSErTfOxpeYGR92XcPzVQXfzqe8sfkF3w1rKCyH2mYV6wK9RuwaBab5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703866692; c=relaxed/simple; bh=L23vdK0/Njo8CkQHnGMi9IHyhwAx6zkPOC5iQZUslaY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JQ3crstbehvSm6wgRusvs1uK7l8Z4jsxI+2JkUvAgIFTmykLEAK2dfjqG5xqTafQMcVcTLGMWZHjVU4ETZNWGgWCGEAusc8NPf5WfxsjEzeuyCs6/gqOooqKBFnGbePcwqeSVouLphNmaXhEBl+WyBoqVufcO+jA6XDIzgMC5R4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-6d9b37f4804so2553570b3a.1; Fri, 29 Dec 2023 08:18:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703866688; x=1704471488; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WyFUOdzdNRg4MUKshhNrm6cOLWhUWYTw42wHqri23/o=; b=PmaMRsEUofRRD+sDpqS5f8NP9KL1fc/sYv3Zn6vZQA9d0lPTO/2qZZFYaqb4cfa+P3 QbNeORUVPLEVpKA4uYTsI2/7rSL9CyndP7mkjcqi5v3J2lmSVJosqpaKyn8Db0L8DsfQ tYNPfFpTG1r9tMZ9nFpsO2h9dsbq+d+NiA9uUSGZDwZXpZoVCdpN08J8GbefLDtawadI 2QCYAXGENi3YkKexRZ5IuoWSM7rUns2hFEhfyNpZer3j0OPzrFj32xwZlQQlxjX/QBke jUrCM6EjwqHLIOhkdIuKCE2mQ96jWCNic/r/3216DtEC1YIn6Dc52feW0MSviXTn8++h vSgQ== X-Gm-Message-State: AOJu0YyhKrcoOUtSwYtnu4/W0e6PDk9KhD3GPDPKd8FUm+6lSBp0D5hC r4qK80h+FmWlrMju3jH2Hn4Hz9q3Vuv1pTEp X-Google-Smtp-Source: AGHT+IGJh5lCWVMKlqqwtNAWQm9nI9/iG91ghFrpBd/3B3tKvVoytaZ72QrDDltz1eMNRTolUnpOsg== X-Received: by 2002:a05:6a20:72a7:b0:196:a12b:1094 with SMTP id o39-20020a056a2072a700b00196a12b1094mr161474pzk.20.1703866688441; Fri, 29 Dec 2023 08:18:08 -0800 (PST) Received: from localhost.localdomain ([149.248.38.156]) by smtp.gmail.com with ESMTPSA id a9-20020a63e409000000b005cdbebd61d8sm15222495pgi.9.2023.12.29.08.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 08:18:07 -0800 (PST) From: YunQiang Su To: gcc-patches@gcc.gnu.org Cc: YunQiang Su Subject: [PATCH v2 1/2] MIPS: add pattern insqisi_extended and inshisi_extended Date: Sat, 30 Dec 2023 00:17:53 +0800 Message-Id: <20231229161754.2802162-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This match pattern allows combination (zero_extract:DI 8, 24, QI) with an sign-extend to 32bit INS instruction on TARGET_64BIT. The problem is that, for SI mode, if the sign-bit is modified by bitops, we will need a sign-extend operation. Since 32bit INS instruction can be sure that result is sign-extended, and the QImode src register is safe for INS, too. (insn 19 18 20 2 (set (zero_extract:DI (reg/v:DI 200 [ val ]) (const_int 8 [0x8]) (const_int 24 [0x18])) (subreg:DI (reg:QI 205) 0)) "../xx.c":7:29 -1 (nil)) (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "../xx.c":7:29 -1 (nil)) Combine try to merge them to: (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (ior:SI (and:SI (subreg:SI (reg/v:DI 200 [ val ]) 0) (const_int 16777215 [0xffffff])) (ashift:SI (subreg:SI (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) 0) (const_int 24 [0x18]))))) "../xx.c":7:29 18 {*insv_extended} (expr_list:REG_DEAD (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) (nil))) Let's accept this pattern. Note: with this patch, we cannot get INS yet: rtx_cost treats that the later one is more expensive than the previous 2. And do similarly for 16/16 pair: (insn 13 12 14 2 (set (zero_extract:DI (reg/v:DI 198 [ val ]) (const_int 16 [0x10]) (const_int 16 [0x10])) (subreg:DI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0)) "xx.c":5:30 286 {*insvdi} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 198 [ val ]) 0))) "xx.c":5:30 241 {extendsidi2} (nil)) ------------> (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (ior:SI (ashift:SI (subreg:SI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0) (const_int 16 [0x10])) (zero_extend:SI (subreg:HI (reg/v:DI 198 [ val ]) 0))))) "xx.c":5:30 284 {*inshisi_extended} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) gcc * config/mips/mips.md (insqisi_extended): New pattern. (inshisi_extended): Ditto. --- gcc/config/mips/mips.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 0666310734e..a4c6d630aeb 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4415,6 +4415,28 @@ (define_insn "*extzv_truncsi_exts" [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_insn "*insqisi_extended" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI + (ior:SI (and:SI (subreg:SI (match_dup 0) 0) + (const_int 16777215)) + (ashift:SI + (subreg:SI (match_operand:QI 1 "register_operand" "d") 0) + (const_int 24)))))] + "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXT_INS" + "ins\t%0,%1,24,8" + [(set_attr "mode" "SI")]) + +(define_insn "*inshisi_extended" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI + (ior:SI + (ashift:SI (subreg:SI (match_operand:HI 1 "register_operand" "d") 0) + (const_int 16)) + (zero_extend:SI (subreg:HI (match_dup 0) 0)))))] + "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXT_INS" + "ins\t%0,%1,16,16" + [(set_attr "mode" "SI")]) (define_expand "insvmisalign" [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand") -- 2.39.2