* [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics
@ 2024-01-02 9:23 Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 01/12] [GCC] arm: vld1q_types_x2 ACLE intrinsics Ezra.Sitorus
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
Add vld1q, vst1, vst1q and vst1 intrinsics to arm port.
Ezra Sitorus (12):
[GCC] arm: vld1q_types_x2 ACLE intrinsics
[GCC] arm: vld1q_types_x3 ACLE intrinsics
[GCC] arm: vld1q_types_x4 ACLE intrinsics
[GCC] arm: vst1_types_x2 ACLE intrinsics
[GCC] arm: vst1_types_x3 ACLE intrinsics
[GCC] arm: vst1_types_x4 ACLE intrinsics
[GCC] arm: vst1q_types_x2 ACLE intrinsics
[GCC] arm: vst1q_types_x3 ACLE intrinsics
[GCC] arm: vst1q_types_x4 ACLE intrinsics
[GCC] arm: vld1_types_x2 ACLE intrinsics
[GCC] arm: vld1_types_x3 ACLE intrinsics
[GCC] arm: vld1_types_x4 ACLE intrinsics
gcc/config/arm/arm_neon.h | 2032 ++++++++++++++---
gcc/config/arm/arm_neon_builtins.def | 12 +
gcc/config/arm/iterators.md | 6 +
gcc/config/arm/neon.md | 249 ++
gcc/config/arm/unspecs.md | 8 +
.../gcc.target/arm/simd/vld1_base_xN_1.c | 176 ++
.../gcc.target/arm/simd/vld1_bf16_xN_1.c | 23 +
.../gcc.target/arm/simd/vld1_fp16_xN_1.c | 23 +
.../gcc.target/arm/simd/vld1_p64_xN_1.c | 23 +
.../gcc.target/arm/simd/vld1q_base_xN_1.c | 183 ++
.../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 24 +
.../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 24 +
.../gcc.target/arm/simd/vld1q_p64_xN_1.c | 24 +
.../gcc.target/arm/simd/vst1_base_xN_1.c | 176 ++
.../gcc.target/arm/simd/vst1_bf16_xN_1.c | 22 +
.../gcc.target/arm/simd/vst1_fp16_xN_1.c | 23 +
.../gcc.target/arm/simd/vst1_p64_xN_1.c | 23 +
.../gcc.target/arm/simd/vst1q_base_xN_1.c | 185 ++
.../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 24 +
.../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 24 +
.../gcc.target/arm/simd/vst1q_p64_xN_1.c | 24 +
21 files changed, 3018 insertions(+), 290 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 01/12] [GCC] arm: vld1q_types_x2 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 02/12] [GCC] arm: vld1q_types_x3 " Ezra.Sitorus
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1q intrinsic for the arm port. This patch adds the
_x2 variants of the vld1q intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
(vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
(vld1q_f16_x2, vld1q_f32_x2): New.
(vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
(vld1q_bf16_x2): New.
* config/arm/arm_neon_builtins.def (vld1_x2): New entries.
* config/arm/neon.md (vld1_x2<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1q_base_xN_1.c: Add new test.
* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new test.
* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new test.
* gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new test.
---
gcc/config/arm/arm_neon.h | 128 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 10 ++
.../gcc.target/arm/simd/vld1q_base_xN_1.c | 67 +++++++++
.../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 14 ++
.../gcc.target/arm/simd/vld1q_p64_xN_1.c | 14 ++
7 files changed, 247 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index cdfdb44259a..3eb41c6bdc8 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10403,6 +10403,15 @@ vld1q_p64 (const poly64_t * __a)
return (poly64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
}
+__extension__ extern __inline poly64x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p64_x2 (const poly64_t * __a)
+{
+ union { poly64x2x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10432,6 +10441,42 @@ vld1q_s64 (const int64_t * __a)
return (int64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
}
+__extension__ extern __inline int8x16x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s8_x2 (const int8_t * __a)
+{
+ union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s16_x2 (const int16_t * __a)
+{
+ union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s32_x2 (const int32_t * __a)
+{
+ union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s64_x2 (const int64_t * __a)
+{
+ union { int64x2x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10448,6 +10493,26 @@ vld1q_f32 (const float32_t * __a)
return (float32x4_t)__builtin_neon_vld1v4sf ((const __builtin_neon_sf *) __a);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f16_x2 (const float16_t * __a)
+{
+ union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f32_x2 (const float32_t * __a)
+{
+ union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8 (const uint8_t * __a)
@@ -10476,6 +10541,42 @@ vld1q_u64 (const uint64_t * __a)
return (uint64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
}
+__extension__ extern __inline uint8x16x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u8_x2 (const uint8_t * __a)
+{
+ union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u16_x2 (const uint16_t * __a)
+{
+ union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u32_x2 (const uint32_t * __a)
+{
+ union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u64_x2 (const uint64_t * __a)
+{
+ union { uint64x2x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8 (const poly8_t * __a)
@@ -10490,6 +10591,24 @@ vld1q_p16 (const poly16_t * __a)
return (poly16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
}
+__extension__ extern __inline poly8x16x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p8_x2 (const poly8_t * __a)
+{
+ union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p16_x2 (const poly16_t * __a)
+{
+ union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)
@@ -19782,6 +19901,15 @@ vld1q_bf16 (const bfloat16_t * __ptr)
return __builtin_neon_vld1v8bf (__ptr);
}
+__extension__ extern __inline bfloat16x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_bf16_x2 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x4x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld2_bf16 (bfloat16_t const * __ptr)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 94b15238123..5fadd255c18 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -298,6 +298,7 @@ VAR1 (TERNOP, vtbx1, v8qi)
VAR1 (TERNOP, vtbx2, v8qi)
VAR1 (TERNOP, vtbx3, v8qi)
VAR1 (TERNOP, vtbx4, v8qi)
+VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR13 (LOAD1, vld1,
v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index d213369ffc3..55049ea549f 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4957,6 +4957,16 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_1reg<q>")]
)
+(define_insn "neon_vld1_x2<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1))]
+ "TARGET_NEON"
+ "vld1.<V_sz_elem>\t%h0, %A1"
+ [(set_attr "type" "neon_load1_2reg<q>")]
+)
+
;; The lane numbers in the RTL are in GCC lane order, having been flipped
;; in arm_expand_neon_args. The lane numbers are restored to architectural
;; lane order here.
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
new file mode 100644
index 00000000000..1d31777afdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -0,0 +1,67 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x16x2_t test_vld1q_u8_x2 (uint8_t * a)
+{
+ return vld1q_u8_x2 (a);
+}
+
+uint16x8x2_t test_vld1q_u16_x2 (uint16_t * a)
+{
+ return vld1q_u16_x2 (a);
+}
+
+uint32x4x2_t test_vld1q_u32_x2 (uint32_t * a)
+{
+ return vld1q_u32_x2 (a);
+}
+
+uint64x2x2_t test_vld1q_u64_x2 (uint64_t * a)
+{
+ return vld1q_u64_x2 (a);
+}
+
+int8x16x2_t test_vld1q_s8_x2 (int8_t * a)
+{
+ return vld1q_s8_x2 (a);
+}
+
+int16x8x2_t test_vld1q_s16_x2 (int16_t * a)
+{
+ return vld1q_s16_x2 (a);
+}
+
+int32x4x2_t test_vld1q_s32_x2 (int32_t * a)
+{
+ return vld1q_s32_x2 (a);
+}
+
+int64x2x2_t test_vld1q_s64_x2 (int64_t * a)
+{
+ return vld1q_s64_x2 (a);
+}
+
+float32x4x2_t test_vld1q_f32_x2 (float32_t * a)
+{
+ return vld1q_f32_x2 (a);
+}
+
+poly8x16x2_t test_vld1q_p8_x2 (poly8_t * a)
+{
+ return vld1q_p8_x2 (a);
+}
+
+poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a)
+{
+ return vld1q_p16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
new file mode 100644
index 00000000000..5f6fc98640e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a)
+{
+ return vld1q_bf16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
new file mode 100644
index 00000000000..aecf491a4de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+float16x8x2_t test_vld1q_f16_x2 (float16_t * a)
+{
+ return vld1q_f16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
new file mode 100644
index 00000000000..04ceb5e4a24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a)
+{
+ return vld1q_p64_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
+
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 02/12] [GCC] arm: vld1q_types_x3 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 01/12] [GCC] arm: vld1q_types_x2 ACLE intrinsics Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 03/12] [GCC] arm: vld1q_types_x4 " Ezra.Sitorus
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1q intrinsic for the arm port. This patch adds the
_x3 variants of the vld1q intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
(vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
(vld1q_f16_x3, vld1q_f32_x3): New.
(vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
(vld1q_bf16_x3): New.
* config/arm/arm_neon_builtins.def (vld1_x3): New entries.
* config/arm/neon.md
(neon_vld1_x3<mode>): New.
(neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
* config/arm/unspecs.md
(UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 128 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 48 +++++++
gcc/config/arm/unspecs.md | 2 +
.../gcc.target/arm/simd/vld1q_base_xN_1.c | 69 +++++++++-
.../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 8 +-
.../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vld1q_p64_xN_1.c | 7 +-
8 files changed, 263 insertions(+), 7 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 3eb41c6bdc8..557873ac028 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10412,6 +10412,15 @@ vld1q_p64_x2 (const poly64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p64_x3 (const poly64_t * __a)
+{
+ union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10477,6 +10486,42 @@ vld1q_s64_x2 (const int64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline int8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s8_x3 (const uint8_t * __a)
+{
+ union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s16_x3 (const uint16_t * __a)
+{
+ union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s32_x3 (const int32_t * __a)
+{
+ union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s64_x3 (const int64_t * __a)
+{
+ union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10513,6 +10558,26 @@ vld1q_f32_x2 (const float32_t * __a)
return __rv.__i;
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f16_x3 (const float16_t * __a)
+{
+ union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f32_x3 (const float32_t * __a)
+{
+ union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8 (const uint8_t * __a)
@@ -10577,6 +10642,42 @@ vld1q_u64_x2 (const uint64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline uint8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u8_x3 (const uint8_t * __a)
+{
+ union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u16_x3 (const uint16_t * __a)
+{
+ union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u32_x3 (const uint32_t * __a)
+{
+ union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u64_x3 (const uint64_t * __a)
+{
+ union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8 (const poly8_t * __a)
@@ -10609,6 +10710,24 @@ vld1q_p16_x2 (const poly16_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p8_x3 (const poly8_t * __a)
+{
+ union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p16_x3 (const poly16_t * __a)
+{
+ union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)
@@ -19910,6 +20029,15 @@ vld1q_bf16_x2 (const bfloat16_t * __ptr)
return __rv.__i;
}
+__extension__ extern __inline bfloat16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_bf16_x3 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x4x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld2_bf16 (bfloat16_t const * __ptr)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 5fadd255c18..57783bd0089 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -299,6 +299,7 @@ VAR1 (TERNOP, vtbx2, v8qi)
VAR1 (TERNOP, vtbx3, v8qi)
VAR1 (TERNOP, vtbx4, v8qi)
VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR13 (LOAD1, vld1,
v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 55049ea549f..235999e152a 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4967,6 +4967,54 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_2reg<q>")]
)
+(define_expand "neon_vld1_x3<mode>"
+ [(match_operand:CI 0 "s_register_operand")
+ (match_operand:CI 1 "neon_struct_operand")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+{
+ rtx mem = adjust_address (operands[1], EImode, 0);
+ emit_insn (gen_neon_vld1x3qa<mode> (operands[0], mem));
+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
+ emit_insn (gen_neon_vld1x3qb<mode> (operands[0], mem, operands[0]));
+ DONE;
+})
+
+(define_insn "neon_vld1x3qa<mode>"
+ [(set (match_operand:CI 0 "s_register_operand" "=w")
+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1X3A))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = gen_rtx_REG (EImode, REGNO (operands[0]));
+ ops[1] = operands[1];
+
+ output_asm_insn ("vld1.<V_sz_elem>\t%h0, %A1", ops);
+ return "";
+}
+ [(set_attr "type" "neon_load1_3reg<q>")]
+)
+
+(define_insn "neon_vld1x3qb<mode>"
+ [(set (match_operand:CI 0 "s_register_operand" "=w")
+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
+ (match_operand:CI 2 "s_register_operand" "0")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1X3B))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = gen_rtx_REG (EImode, REGNO (operands[0]) + 6);
+ ops[1] = operands[1];
+
+ output_asm_insn ("vld1.<V_sz_elem>\t%h0, %A1", ops);
+ return "";
+}
+ [(set_attr "type" "neon_load1_3reg<q>")]
+)
+
;; The lane numbers in the RTL are in GCC lane order, having been flipped
;; in arm_expand_neon_args. The lane numbers are restored to architectural
;; lane order here.
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 4713ec840ab..e777edceef5 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -342,6 +342,8 @@
UNSPEC_VHSUB_S
UNSPEC_VHSUB_U
UNSPEC_VLD1
+ UNSPEC_VLD1X3A
+ UNSPEC_VLD1X3B
UNSPEC_VLD1_LANE
UNSPEC_VLD2
UNSPEC_VLD2_DUP
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index 1d31777afdf..117bc58c161 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -60,8 +60,69 @@ poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a)
return vld1q_p16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+uint8x16x3_t test_vld1q_u8_x3 (uint8_t * a)
+{
+ return vld1q_u8_x3 (a);
+}
+
+uint16x8x3_t test_vld1q_u16_x3 (uint16_t * a)
+{
+ return vld1q_u16_x3 (a);
+}
+
+uint32x4x3_t test_vld1q_u32_x3 (uint32_t * a)
+{
+ return vld1q_u32_x3 (a);
+}
+
+uint64x2x3_t test_vld1q_u64_x3 (uint64_t * a)
+{
+ return vld1q_u64_x3 (a);
+}
+
+int8x16x3_t test_vld1q_s8_x3 (int8_t * a)
+{
+ return vld1q_s8_x3 (a);
+}
+
+int16x8x3_t test_vld1q_s16_x3 (int16_t * a)
+{
+ return vld1q_s16_x3 (a);
+}
+
+int32x4x3_t test_vld1q_s32_x3 (int32_t * a)
+{
+ return vld1q_s32_x3 (a);
+}
+
+int64x2x3_t test_vld1q_s64_x3 (int64_t * a)
+{
+ return vld1q_s64_x3 (a);
+}
+
+float32x4x3_t test_vld1q_f32_x3 (float32_t * a)
+{
+ return vld1q_f32_x3 (a);
+}
+
+poly8x16x3_t test_vld1q_p8_x3 (poly8_t * a)
+{
+ return vld1q_p8_x3 (a);
+}
+
+poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a)
+{
+ return vld1q_p16_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
index 5f6fc98640e..75b61f1ecf0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
@@ -10,4 +10,10 @@ bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a)
return vld1q_bf16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a)
+{
+ return vld1q_bf16_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
index aecf491a4de..9032048bed5 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
@@ -10,5 +10,10 @@ float16x8x2_t test_vld1q_f16_x2 (float16_t * a)
return vld1q_f16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+float16x8x3_t test_vld1q_f16_x3 (float16_t * a)
+{
+ return vld1q_f16_x3 (a);
+}
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
index 04ceb5e4a24..aabc31bbd08 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
@@ -10,5 +10,10 @@ poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a)
return vld1q_p64_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
+poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a)
+{
+ return vld1q_p64_x3 (a);
+}
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 1 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 03/12] [GCC] arm: vld1q_types_x4 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 01/12] [GCC] arm: vld1q_types_x2 ACLE intrinsics Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 02/12] [GCC] arm: vld1q_types_x3 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 04/12] [GCC] arm: vst1_types_x2 " Ezra.Sitorus
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1q intrinsic for the arm port. This patch adds the
_x4 variants of the vld1q intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
(vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
(vld1q_f16_x4, vld1q_f32_x4): New.
(vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
(vld1q_bf16_x4): New.
* config/arm/arm_neon_builtins.def (vld1_x4): New entries.
* config/arm/neon.md
(neon_vld1_x4<mode>): New.
(neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
* config/arm/unspecs.md
(UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1q_base_xN_1.c: Updated.
* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1q_p64_xN_1.c: Updated.
---
gcc/config/arm/arm_neon.h | 128 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 48 +++++++
gcc/config/arm/unspecs.md | 2 +
.../gcc.target/arm/simd/vld1q_base_xN_1.c | 71 ++++++++--
.../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 9 +-
.../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 9 +-
.../gcc.target/arm/simd/vld1q_p64_xN_1.c | 9 +-
8 files changed, 263 insertions(+), 14 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 557873ac028..c03be9912f8 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10421,6 +10421,15 @@ vld1q_p64_x3 (const poly64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p64_x4 (const poly64_t * __a)
+{
+ union { poly64x2x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10522,6 +10531,42 @@ vld1q_s64_x3 (const int64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline int8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s8_x4 (const uint8_t * __a)
+{
+ union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s16_x4 (const uint16_t * __a)
+{
+ union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s32_x4 (const int32_t * __a)
+{
+ union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s64_x4 (const int64_t * __a)
+{
+ union { int64x2x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10578,6 +10623,26 @@ vld1q_f32_x3 (const float32_t * __a)
return __rv.__i;
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f16_x4 (const float16_t * __a)
+{
+ union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f32_x4 (const float32_t * __a)
+{
+ union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8 (const uint8_t * __a)
@@ -10678,6 +10743,42 @@ vld1q_u64_x3 (const uint64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline uint8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u8_x4 (const uint8_t * __a)
+{
+ union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u16_x4 (const uint16_t * __a)
+{
+ union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u32_x4 (const uint32_t * __a)
+{
+ union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u64_x4 (const uint64_t * __a)
+{
+ union { uint64x2x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8 (const poly8_t * __a)
@@ -10728,6 +10829,24 @@ vld1q_p16_x3 (const poly16_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p8_x4 (const poly8_t * __a)
+{
+ union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p16_x4 (const poly16_t * __a)
+{
+ union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)
@@ -20038,6 +20157,15 @@ vld1q_bf16_x3 (const bfloat16_t * __ptr)
return __rv.__i;
}
+__extension__ extern __inline bfloat16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_bf16_x4 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x4x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld2_bf16 (bfloat16_t const * __ptr)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 57783bd0089..f4001b298c4 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -300,6 +300,7 @@ VAR1 (TERNOP, vtbx3, v8qi)
VAR1 (TERNOP, vtbx4, v8qi)
VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR13 (LOAD1, vld1,
v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 235999e152a..e9c68b9baad 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5015,6 +5015,54 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_3reg<q>")]
)
+(define_expand "neon_vld1_x4<mode>"
+ [(match_operand:XI 0 "s_register_operand")
+ (match_operand:XI 1 "neon_struct_operand")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+{
+ rtx mem = adjust_address (operands[1], OImode, 0);
+ emit_insn (gen_neon_vld1x4qa<mode> (operands[0], mem));
+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
+ emit_insn (gen_neon_vld1x4qb<mode> (operands[0], mem, operands[0]));
+ DONE;
+})
+
+(define_insn "neon_vld1x4qa<mode>"
+ [(set (match_operand:XI 0 "s_register_operand" "=w")
+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1X4A))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = gen_rtx_REG (OImode, REGNO (operands[0]));
+ ops[1] = operands[1];
+
+ output_asm_insn ("vld1.<V_sz_elem>\t%h0, %A1", ops);
+ return "";
+}
+ [(set_attr "type" "neon_load1_4reg<q>")]
+)
+
+(define_insn "neon_vld1x4qb<mode>"
+ [(set (match_operand:XI 0 "s_register_operand" "=w")
+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (match_operand:XI 2 "s_register_operand" "0")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1X4B))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = gen_rtx_REG (OImode, REGNO (operands[0]) + 8);
+ ops[1] = operands[1];
+
+ output_asm_insn ("vld1.<V_sz_elem>\t%h0, %A1", ops);
+ return "";
+}
+ [(set_attr "type" "neon_load1_4reg<q>")]
+)
+
;; The lane numbers in the RTL are in GCC lane order, having been flipped
;; in arm_expand_neon_args. The lane numbers are restored to architectural
;; lane order here.
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index e777edceef5..4753968d52f 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -344,6 +344,8 @@
UNSPEC_VLD1
UNSPEC_VLD1X3A
UNSPEC_VLD1X3B
+ UNSPEC_VLD1X4A
+ UNSPEC_VLD1X4B
UNSPEC_VLD1_LANE
UNSPEC_VLD2
UNSPEC_VLD2_DUP
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index 117bc58c161..01b29b60084 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -115,14 +115,69 @@ poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a)
return vld1q_p16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+uint8x16x4_t test_vld1q_u8_x4 (uint8_t * a)
+{
+ return vld1q_u8_x4 (a);
+}
+
+uint16x8x4_t test_vld1q_u16_x4 (uint16_t * a)
+{
+ return vld1q_u16_x4 (a);
+}
+
+uint32x4x4_t test_vld1q_u32_x4 (uint32_t * a)
+{
+ return vld1q_u32_x4 (a);
+}
+
+uint64x2x4_t test_vld1q_u64_x4 (uint64_t * a)
+{
+ return vld1q_u64_x4 (a);
+}
+
+int8x16x4_t test_vld1q_s8_x4 (int8_t * a)
+{
+ return vld1q_s8_x4 (a);
+}
+
+int16x8x4_t test_vld1q_s16_x4 (int16_t * a)
+{
+ return vld1q_s16_x4 (a);
+}
+
+int32x4x4_t test_vld1q_s32_x4 (int32_t * a)
+{
+ return vld1q_s32_x4 (a);
+}
+
+int64x2x4_t test_vld1q_s64_x4 (int64_t * a)
+{
+ return vld1q_s64_x4 (a);
+}
+
+float32x4x4_t test_vld1q_f32_x4 (float32_t * a)
+{
+ return vld1q_f32_x4 (a);
+}
+
+poly8x16x4_t test_vld1q_p8_x4 (poly8_t * a)
+{
+ return vld1q_p8_x4 (a);
+}
+
+poly16x8x4_t test_vld1q_p16_x4 (poly16_t * a)
+{
+ return vld1q_p16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
index 75b61f1ecf0..21db3520c1a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
@@ -15,5 +15,10 @@ bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a)
return vld1q_bf16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
+bfloat16x8x4_t test_vld1q_bf16_x4 (bfloat16_t * a)
+{
+ return vld1q_bf16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
index 9032048bed5..3838cd072ea 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
@@ -15,5 +15,10 @@ float16x8x3_t test_vld1q_f16_x3 (float16_t * a)
return vld1q_f16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
+float16x8x4_t test_vld1q_f16_x4 (float16_t * a)
+{
+ return vld1q_f16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
index aabc31bbd08..d359a5a85a2 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
@@ -15,5 +15,10 @@ poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a)
return vld1q_p64_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 1 } } */
+poly64x2x4_t test_vld1q_p64_x4 (poly64_t * a)
+{
+ return vld1q_p64_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 04/12] [GCC] arm: vst1_types_x2 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (2 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 03/12] [GCC] arm: vld1q_types_x4 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 05/12] [GCC] arm: vst1_types_x3 " Ezra.Sitorus
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x2 variants of the vst1 intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
(vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
(vst1_f16_x2, vst1_f32_x2): New.
(vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
(vst1_bf16_x2): New.
* config/arm/arm_neon_builtins.def (vst1_x2): New entries.
* config/arm/neon.md (vst1_x2<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 10 ++
.../gcc.target/arm/simd/vst1_base_xN_1.c | 67 ++++++++++
.../gcc.target/arm/simd/vst1_bf16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vst1_fp16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vst1_p64_xN_1.c | 13 ++
7 files changed, 231 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index c03be9912f8..60f1077752c 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11242,6 +11242,14 @@ vst1_p64 (poly64_t * __a, poly64x1_t __b)
__builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x2 (poly64_t * __a, poly64x1x2_t __b)
+{
+ union { poly64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11271,6 +11279,38 @@ vst1_s64 (int64_t * __a, int64x1_t __b)
__builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x2 (int8_t * __a, int8x8x2_t __b)
+{
+ union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x2 (int16_t * __a, int16x4x2_t __b)
+{
+ union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x2 (int32_t * __a, int32x2x2_t __b)
+{
+ union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
+{
+ union { int64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11287,6 +11327,24 @@ vst1_f32 (float32_t * __a, float32x2_t __b)
__builtin_neon_vst1v2sf ((__builtin_neon_sf *) __a, __b);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x2 (float16_t * __a, float16x4x2_t __b)
+{
+ union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x2 (float32_t * __a, float32x2x2_t __b)
+{
+ union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11315,6 +11373,38 @@ vst1_u64 (uint64_t * __a, uint64x1_t __b)
__builtin_neon_vst1di ((__builtin_neon_di *) __a, (int64x1_t) __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x2 (uint8_t * __a, uint8x8x2_t __b)
+{
+ union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x2 (uint16_t * __a, uint16x4x2_t __b)
+{
+ union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x2 (uint32_t * __a, uint32x2x2_t __b)
+{
+ union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x2 (uint64_t * __a, uint64x1x2_t __b)
+{
+ union { uint64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11329,6 +11419,22 @@ vst1_p16 (poly16_t * __a, poly16x4_t __b)
__builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x2 (poly8_t * __a, poly8x8x2_t __b)
+{
+ union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x2 (poly16_t * __a, poly16x4x2_t __b)
+{
+ union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline void
@@ -20070,6 +20176,14 @@ vst1_bf16 (bfloat16_t * __a, bfloat16x4_t __b)
__builtin_neon_vst1v4bf (__a, __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x2 (bfloat16_t * __a, bfloat16x4x2_t __b)
+{
+ union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+ __builtin_neon_vst1_x2v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index f4001b298c4..ab88b68a8f4 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -311,6 +311,7 @@ VAR10 (LOAD1, vld1_dup,
VAR14 (STORE1, vst1,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
+VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index e9c68b9baad..ac709a25506 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5172,6 +5172,16 @@ if (BYTES_BIG_ENDIAN)
"vst1.<V_sz_elem>\t%h1, %A0"
[(set_attr "type" "neon_store1_1reg<q>")])
+(define_insn "neon_vst1_x2<mode>"
+ [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+ (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1))]
+ "TARGET_NEON"
+ "vst1.<V_sz_elem>\t%h1, %A0"
+ [(set_attr "type" "neon_store1_2reg<q>")]
+)
+
;; see comment on neon_vld1_lane for reason why the lane numbers are reversed
;; here on big endian targets.
(define_insn "neon_vst1_lane<mode>"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
new file mode 100644
index 00000000000..575897fa422
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -0,0 +1,67 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_u8_x2 (uint8_t * ptr, uint8x8x2_t val)
+{
+ vst1_u8_x2 (ptr, val);
+}
+
+void test_vst1_u16_x2 (uint16_t * ptr, uint16x4x2_t val)
+{
+ vst1_u16_x2 (ptr, val);
+}
+
+void test_vst1_u32_x2 (uint32_t * ptr, uint32x2x2_t val)
+{
+ vst1_u32_x2 (ptr, val);
+}
+
+void test_vst1_u64_x2 (uint64_t * ptr, uint64x1x2_t val)
+{
+ vst1_u64_x2 (ptr, val);
+}
+
+void test_vst1_s8_x2 (int8_t * ptr, int8x8x2_t val)
+{
+ vst1_s8_x2 (ptr, val);
+}
+
+void test_vst1_s16_x2 (int16_t * ptr, int16x4x2_t val)
+{
+ vst1_s16_x2 (ptr, val);
+}
+
+void test_vst1_s32_x2 (int32_t * ptr, int32x2x2_t val)
+{
+ vst1_s32_x2 (ptr, val);
+}
+
+void test_vst1_s64_x2 (int64_t * ptr, int64x1x2_t val)
+{
+ vst1_s64_x2 (ptr, val);
+}
+
+void test_vst1_f32_x2 (float32_t * ptr, float32x2x2_t val)
+{
+ vst1_f32_x2 (ptr, val);
+}
+
+void test_vst1_p8_x2 (poly8_t * ptr, poly8x8x2_t val)
+{
+ vst1_p8_x2 (ptr, val);
+}
+
+void test_vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val)
+{
+ vst1_p16_x2 (ptr, val);
+}
+
+
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
new file mode 100644
index 00000000000..213fd20ee65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_bf16_x2 (bfloat16_t * ptr, bfloat16x4x2_t val)
+{
+ vst1_bf16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
new file mode 100644
index 00000000000..523aec92db2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vst1_f16_x2 (float16_t * ptr, float16x4x2_t val)
+{
+ vst1_f16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
new file mode 100644
index 00000000000..f590ebd7b94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val)
+{
+ vst1_p64_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
\ No newline at end of file
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 05/12] [GCC] arm: vst1_types_x3 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (3 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 04/12] [GCC] arm: vst1_types_x2 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 06/12] [GCC] arm: vst1_types_x4 " Ezra.Sitorus
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x3 variants of the vst1 intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
(vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
(vst1_f16_x3, vst1_f32_x3): New.
(vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
(vst1_bf16_x3): New.
* config/arm/arm_neon_builtins.def (vst1_x3): New entries.
* config/arm/neon.md (vst1_x3<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1_base_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_bf16_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_fp16_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_p64_xN_1.c: Updated.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 10 ++
.../gcc.target/arm/simd/vst1_base_xN_1.c | 63 +++++++++-
.../gcc.target/arm/simd/vst1_bf16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vst1_fp16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vst1_p64_xN_1.c | 7 +-
7 files changed, 202 insertions(+), 7 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 60f1077752c..e76be3516d9 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11250,6 +11250,14 @@ vst1_p64_x2 (poly64_t * __a, poly64x1x2_t __b)
__builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x3 (poly64_t * __a, poly64x1x3_t __b)
+{
+ union { poly64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11311,6 +11319,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
__builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
+{
+ union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x3 (int16_t * __a, int16x4x3_t __b)
+{
+ union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x3 (int32_t * __a, int32x2x3_t __b)
+{
+ union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x3 (int64_t * __a, int64x1x3_t __b)
+{
+ union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11345,6 +11385,24 @@ vst1_f32_x2 (float32_t * __a, float32x2x2_t __b)
__builtin_neon_vst1_x2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x3 (float16_t * __a, float16x4x3_t __b)
+{
+ union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x3 (float32_t * __a, float32x2x3_t __b)
+{
+ union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11405,6 +11463,38 @@ vst1_u64_x2 (uint64_t * __a, uint64x1x2_t __b)
__builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x3 (uint8_t * __a, uint8x8x3_t __b)
+{
+ union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x3 (uint16_t * __a, uint16x4x3_t __b)
+{
+ union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x3 (uint32_t * __a, uint32x2x3_t __b)
+{
+ union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x3 (uint64_t * __a, uint64x1x3_t __b)
+{
+ union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11435,6 +11525,22 @@ vst1_p16_x2 (poly16_t * __a, poly16x4x2_t __b)
__builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x3 (poly8_t * __a, poly8x8x3_t __b)
+{
+ union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x3 (poly16_t * __a, poly16x4x3_t __b)
+{
+ union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline void
@@ -20184,6 +20290,14 @@ vst1_bf16_x2 (bfloat16_t * __a, bfloat16x4x2_t __b)
__builtin_neon_vst1_x2v4bf ((__builtin_neon_bf *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x3 (bfloat16_t * __a, bfloat16x4x3_t __b)
+{
+ union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+ __builtin_neon_vst1_x3v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index ab88b68a8f4..5725cd33b8c 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -312,6 +312,7 @@ VAR14 (STORE1, vst1,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index ac709a25506..97bac2d83f4 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5182,6 +5182,16 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_store1_2reg<q>")]
)
+(define_insn "neon_vst1_x3<mode>"
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+ (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1))]
+ "TARGET_NEON"
+ "vst1.<V_sz_elem>\t%h1, %A0"
+ [(set_attr "type" "neon_store1_3reg<q>")]
+)
+
;; see comment on neon_vld1_lane for reason why the lane numbers are reversed
;; here on big endian targets.
(define_insn "neon_vst1_lane<mode>"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
index 575897fa422..5f820a6a496 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -60,8 +60,63 @@ void test_vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val)
vst1_p16_x2 (ptr, val);
}
+void test_vst1_u8_x3 (uint8_t * ptr, uint8x8x3_t val)
+{
+ vst1_u8_x3 (ptr, val);
+}
+
+void test_vst1_u16_x3 (uint16_t * ptr, uint16x4x3_t val)
+{
+ vst1_u16_x3 (ptr, val);
+}
+
+void test_vst1_u32_x3 (uint32_t * ptr, uint32x2x3_t val)
+{
+ vst1_u32_x3 (ptr, val);
+}
+
+void test_vst1_u64_x3 (uint64_t * ptr, uint64x1x3_t val)
+{
+ vst1_u64_x3 (ptr, val);
+}
+
+void test_vst1_s8_x3 (int8_t * ptr, int8x8x3_t val)
+{
+ vst1_s8_x3 (ptr, val);
+}
+
+void test_vst1_s16_x3 (int16_t * ptr, int16x4x3_t val)
+{
+ vst1_s16_x3 (ptr, val);
+}
+
+void test_vst1_s32_x3 (int32_t * ptr, int32x2x3_t val)
+{
+ vst1_s32_x3 (ptr, val);
+}
+
+void test_vst1_s64_x3 (int64_t * ptr, int64x1x3_t val)
+{
+ vst1_s64_x3 (ptr, val);
+}
+
+void test_vst1_f32_x3 (float32_t * ptr, float32x2x3_t val)
+{
+ vst1_f32_x3 (ptr, val);
+}
+
+void test_vst1_p8_x3 (poly8_t * ptr, poly8x8x3_t val)
+{
+ vst1_p8_x3 (ptr, val);
+}
+
+void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)
+{
+ vst1_p16_x3 (ptr, val);
+}
+
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
index 213fd20ee65..a3a00ead468 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_bf16_x2 (bfloat16_t * ptr, bfloat16x4x2_t val)
vst1_bf16_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val)
+{
+ vst1_bf16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
index 523aec92db2..0a6863e24c6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_f16_x2 (float16_t * ptr, float16x4x2_t val)
vst1_f16_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)
+{
+ vst1_f16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
index f590ebd7b94..5dbd6049bc9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val)
vst1_p64_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
\ No newline at end of file
+void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)
+{
+ vst1_p64_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
\ No newline at end of file
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 06/12] [GCC] arm: vst1_types_x4 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (4 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 05/12] [GCC] arm: vst1_types_x3 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 07/12] [GCC] arm: vst1q_types_x2 " Ezra.Sitorus
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x4 variants of the vst1 intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
(vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
(vst1_f16_x4, vst1_f32_x4): New.
(vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
(vst1_bf16_x4): New.
* config/arm/arm_neon_builtins.def (vst1_x4): New entries.
* config/arm/neon.md (vst1_x4<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1_base_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_bf16_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_fp16_xN_1.c: Updated.
* gcc.target/arm/simd/vst1_p64_xN_1.c: Updated.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 10 ++
.../gcc.target/arm/simd/vst1_base_xN_1.c | 62 +++++++++-
.../gcc.target/arm/simd/vst1_bf16_xN_1.c | 6 +-
.../gcc.target/arm/simd/vst1_fp16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vst1_p64_xN_1.c | 7 +-
7 files changed, 200 insertions(+), 7 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index e76be3516d9..c9bdda39663 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11258,6 +11258,14 @@ vst1_p64_x3 (poly64_t * __a, poly64x1x3_t __b)
__builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x4 (poly64_t * __a, poly64x1x4_t __b)
+{
+ union { poly64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11351,6 +11359,38 @@ vst1_s64_x3 (int64_t * __a, int64x1x3_t __b)
__builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x4 (int8_t * __a, int8x8x4_t __b)
+{
+ union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x4 (int16_t * __a, int16x4x4_t __b)
+{
+ union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x4 (int32_t * __a, int32x2x4_t __b)
+{
+ union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x4 (int64_t * __a, int64x1x4_t __b)
+{
+ union { int64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11403,6 +11443,24 @@ vst1_f32_x3 (float32_t * __a, float32x2x3_t __b)
__builtin_neon_vst1_x3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x4 (float16_t * __a, float16x4x4_t __b)
+{
+ union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x4 (float32_t * __a, float32x2x4_t __b)
+{
+ union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11495,6 +11553,38 @@ vst1_u64_x3 (uint64_t * __a, uint64x1x3_t __b)
__builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x4 (uint8_t * __a, uint8x8x4_t __b)
+{
+ union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x4 (uint16_t * __a, uint16x4x4_t __b)
+{
+ union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x4 (uint32_t * __a, uint32x2x4_t __b)
+{
+ union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x4 (uint64_t * __a, uint64x1x4_t __b)
+{
+ union { uint64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11541,6 +11631,22 @@ vst1_p16_x3 (poly16_t * __a, poly16x4x3_t __b)
__builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x4 (poly8_t * __a, poly8x8x4_t __b)
+{
+ union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x4 (poly16_t * __a, poly16x4x4_t __b)
+{
+ union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline void
@@ -20298,6 +20404,14 @@ vst1_bf16_x3 (bfloat16_t * __a, bfloat16x4x3_t __b)
__builtin_neon_vst1_x3v4bf ((__builtin_neon_bf *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x4 (bfloat16_t * __a, bfloat16x4x4_t __b)
+{
+ union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1_x4v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 5725cd33b8c..cb6d650c2e4 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -313,6 +313,7 @@ VAR14 (STORE1, vst1,
v4bf, v8bf)
VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 97bac2d83f4..96078aadcd5 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5192,6 +5192,16 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_store1_3reg<q>")]
)
+(define_insn "neon_vst1_x4<mode>"
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1))]
+ "TARGET_NEON"
+ "vst1.<V_sz_elem>\t%h1, %A0"
+ [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
;; see comment on neon_vld1_lane for reason why the lane numbers are reversed
;; here on big endian targets.
(define_insn "neon_vst1_lane<mode>"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
index 5f820a6a496..04ca6583552 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -115,8 +115,62 @@ void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)
vst1_p16_x3 (ptr, val);
}
+void test_vst1_u8_x4 (uint8_t * ptr, uint8x8x4_t val)
+{
+ vst1_u8_x4 (ptr, val);
+}
+
+void test_vst1_u16_x4 (uint16_t * ptr, uint16x4x4_t val)
+{
+ vst1_u16_x4 (ptr, val);
+}
+
+void test_vst1_u32_x4 (uint32_t * ptr, uint32x2x4_t val)
+{
+ vst1_u32_x4 (ptr, val);
+}
+
+void test_vst1_u64_x4 (uint64_t * ptr, uint64x1x4_t val)
+{
+ vst1_u64_x4 (ptr, val);
+}
+
+void test_vst1_s8_x4 (int8_t * ptr, int8x8x4_t val)
+{
+ vst1_s8_x4 (ptr, val);
+}
+
+void test_vst1_s16_x4 (int16_t * ptr, int16x4x4_t val)
+{
+ vst1_s16_x4 (ptr, val);
+}
+
+void test_vst1_s32_x4 (int32_t * ptr, int32x2x4_t val)
+{
+ vst1_s32_x4 (ptr, val);
+}
+
+void test_vst1_s64_x4 (int64_t * ptr, int64x1x4_t val)
+{
+ vst1_s64_x4 (ptr, val);
+}
+
+void test_vst1_f32_x4 (float32_t * ptr, float32x2x4_t val)
+{
+ vst1_f32_x4 (ptr, val);
+}
+
+void test_vst1_p8_x4 (poly8_t * ptr, poly8x8x4_t val)
+{
+ vst1_p8_x4 (ptr, val);
+}
+
+void test_vst1_p16_x4 (poly16_t * ptr, poly16x4x4_t val)
+{
+ vst1_p16_x4 (ptr, val);
+}
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
index a3a00ead468..d919c7d060d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -15,4 +15,8 @@ void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val)
vst1_bf16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+void test_vst1_bf16_x4 (bfloat16_t * ptr, bfloat16x4x4_t val)
+{
+ vst1_bf16_x4 (ptr, val);
+}
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
index 0a6863e24c6..3d1d1eb7ad1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)
vst1_f16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+void test_vst1_f16_x4 (float16_t * ptr, float16x4x4_t val)
+{
+ vst1_f16_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
index 5dbd6049bc9..62912143481 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)
vst1_p64_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
\ No newline at end of file
+void test_vst1_p64_x4 (poly64_t * ptr, poly64x1x4_t val)
+{
+ vst1_p64_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */
\ No newline at end of file
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 07/12] [GCC] arm: vst1q_types_x2 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (5 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 06/12] [GCC] arm: vst1_types_x4 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 08/12] [GCC] arm: vst1q_types_x3 " Ezra.Sitorus
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1q intrinsic for the arm port. This patch adds the
_x2 variants of the vst1q intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
(vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
(vst1q_f16_x2, vst1q_f32_x2): New.
(vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
(vst1q_bf16_x2): New.
* config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
* config/arm/neon.md
(neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
neon_vst1_x2<mode>.
* config/arm/iterators.md
(VMEMX2): New mode iterator.
(VMEMX2_q): New mode attribute.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/iterators.md | 6 +
gcc/config/arm/neon.md | 6 +-
.../gcc.target/arm/simd/vst1q_base_xN_1.c | 70 +++++++++++
.../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vst1q_p64_xN_1.c | 13 ++
8 files changed, 233 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index c9bdda39663..1c447b6d42f 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11327,6 +11327,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
__builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x2 (int8_t * __a, int8x16x2_t __b)
+{
+ union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x2 (int16_t * __a, int16x8x2_t __b)
+{
+ union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x2 (int32_t * __a, int32x4x2_t __b)
+{
+ union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b)
+{
+ union { int64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
@@ -11656,6 +11688,14 @@ vst1q_p64 (poly64_t * __a, poly64x2_t __b)
__builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b)
+{
+ union { poly64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11701,6 +11741,24 @@ vst1q_f32 (float32_t * __a, float32x4_t __b)
__builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x2 (float16_t * __a, float16x8x2_t __b)
+{
+ union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v8hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b)
+{
+ union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v4sf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_u8 (uint8_t * __a, uint8x16_t __b)
@@ -11729,6 +11787,38 @@ vst1q_u64 (uint64_t * __a, uint64x2_t __b)
__builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t __b)
+{
+ union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t __b)
+{
+ union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t __b)
+{
+ union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b)
+{
+ union { uint64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_p8 (poly8_t * __a, poly8x16_t __b)
@@ -11743,6 +11833,22 @@ vst1q_p16 (poly16_t * __a, poly16x8_t __b)
__builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t __b)
+{
+ union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b)
+{
+ union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
@@ -20419,6 +20525,14 @@ vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
__builtin_neon_vst1v8bf (__a, __b);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b)
+{
+ union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x2v8bf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index cb6d650c2e4..d44abb80139 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -312,6 +312,7 @@ VAR14 (STORE1, vst1,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR14 (STORE1LANE, vst1_lane,
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index a9803538101..6c5a80d9348 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -141,6 +141,9 @@
;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
(define_mode_iterator VTAB [TI EI OI])
+;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q.
+(define_mode_iterator VMEMX2 [TI OI])
+
;; Widenable modes.
(define_mode_iterator VW [V8QI V4HI V2SI])
@@ -1533,6 +1536,9 @@
;; vtbl<n> suffix for NEON vector modes.
(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
+;; Suffix for x2 variants of vld1 and vst1.
+(define_mode_attr VMEMX2_q [(TI "") (OI "q")])
+
;; fp16 or bf16 marker for 16-bit float modes.
(define_mode_attr fporbf [(HF "fp16") (BF "bf16")])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 96078aadcd5..270130c4086 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5172,9 +5172,9 @@ if (BYTES_BIG_ENDIAN)
"vst1.<V_sz_elem>\t%h1, %A0"
[(set_attr "type" "neon_store1_1reg<q>")])
-(define_insn "neon_vst1_x2<mode>"
- [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
- (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+(define_insn "neon_vst1<VMEMX2_q>_x2<VDQX:mode>"
+ [(set (match_operand:VMEMX2 0 "neon_struct_operand" "=Um")
+ (unspec:VMEMX2 [(match_operand:VMEMX2 1 "s_register_operand" "w")
(unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VST1))]
"TARGET_NEON"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
new file mode 100644
index 00000000000..232feafade0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
@@ -0,0 +1,70 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+
+void test_vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val)
+{
+ vst1q_u8_x2 (ptr, val);
+}
+
+void test_vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val)
+{
+ vst1q_u16_x2 (ptr, val);
+}
+
+void test_vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val)
+{
+ vst1q_u32_x2 (ptr, val);
+}
+
+void test_vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val)
+{
+ vst1q_u64_x2 (ptr, val);
+}
+
+void test_vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val)
+{
+ vst1q_s8_x2 (ptr, val);
+}
+
+void test_vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val)
+{
+ vst1q_s16_x2 (ptr, val);
+}
+
+void test_vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val)
+{
+ vst1q_s32_x2 (ptr, val);
+}
+
+void test_vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val)
+{
+ vst1q_s64_x2 (ptr, val);
+}
+
+void test_vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val)
+{
+ vst1q_f32_x2 (ptr, val);
+}
+
+void test_vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val)
+{
+ vst1q_p8_x2 (ptr, val);
+}
+
+void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val)
+{
+ vst1q_p16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
new file mode 100644
index 00000000000..2a4579f0aae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val)
+{
+ vst1q_bf16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
new file mode 100644
index 00000000000..61a7e558c48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val)
+{
+ vst1q_f16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
new file mode 100644
index 00000000000..82f3dad293c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val)
+{
+ vst1q_p64_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 08/12] [GCC] arm: vst1q_types_x3 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (6 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 07/12] [GCC] arm: vst1q_types_x2 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 09/12] [GCC] arm: vst1q_types_x4 " Ezra.Sitorus
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1q intrinsic for the arm port. This patch adds the
_x3 variants of the vst1q intrinsic.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
(vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
(vst1q_f16_x3, vst1q_f32_x3): New.
(vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
(vst1q_bf16_x3): New.
* config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
* config/arm/neon.md
(neon_vst1q_x3<mode>): New.
(neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
* config/arm/unspecs.md
(UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 47 ++++++++
gcc/config/arm/unspecs.md | 2 +
.../gcc.target/arm/simd/vst1q_base_xN_1.c | 68 ++++++++++-
.../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 8 +-
.../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 8 +-
.../gcc.target/arm/simd/vst1q_p64_xN_1.c | 8 +-
8 files changed, 249 insertions(+), 7 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 1c447b6d42f..5cec7dd876f 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11359,6 +11359,38 @@ vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b)
__builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x3 (int8_t * __a, int8x16x3_t __b)
+{
+ union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x3 (int16_t * __a, int16x8x3_t __b)
+{
+ union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x3 (int32_t * __a, int32x4x3_t __b)
+{
+ union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b)
+{
+ union { int64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
@@ -11696,6 +11728,14 @@ vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b)
__builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b)
+{
+ union { poly64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11759,6 +11799,24 @@ vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b)
__builtin_neon_vst1q_x2v4sf (__a, __bu.__o);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x3 (float16_t * __a, float16x8x3_t __b)
+{
+ union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v8hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b)
+{
+ union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v4sf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_u8 (uint8_t * __a, uint8x16_t __b)
@@ -11819,6 +11877,38 @@ vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b)
__builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x3 (uint8_t * __a, uint8x16x3_t __b)
+{
+ union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x3 (uint16_t * __a, uint16x8x3_t __b)
+{
+ union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x3 (uint32_t * __a, uint32x4x3_t __b)
+{
+ union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b)
+{
+ union { uint64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_p8 (poly8_t * __a, poly8x16_t __b)
@@ -11849,6 +11939,22 @@ vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b)
__builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x3 (poly8_t * __a, poly8x16x3_t __b)
+{
+ union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b)
+{
+ union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
@@ -20533,6 +20639,14 @@ vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b)
__builtin_neon_vst1q_x2v8bf (__a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b)
+{
+ union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+ __builtin_neon_vst1q_x3v8bf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index d44abb80139..f8ff87c0c7a 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -314,6 +314,7 @@ VAR14 (STORE1, vst1,
VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 270130c4086..a311ee0c997 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5192,6 +5192,53 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_store1_3reg<q>")]
)
+(define_expand "neon_vst1q_x3<mode>"
+ [(match_operand:CI 0 "neon_struct_operand")
+ (match_operand:CI 1 "s_register_operand")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+{
+ rtx mem = adjust_address (operands[0], EImode, 0);
+ emit_insn (gen_neon_vst1x3qa<mode> (mem, operands[1]));
+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
+ emit_insn (gen_neon_vst1x3qb<mode> (mem, operands[1]));
+ DONE;
+})
+
+(define_insn "neon_vst1x3qa<mode>"
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1X3A))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (EImode, REGNO (operands[1]));
+
+ output_asm_insn ("vst1.<V_sz_elem>\t%h1, %A0", ops);
+ return "";
+}
+ [(set_attr "type" "neon_store1_3reg<q>")]
+)
+
+(define_insn "neon_vst1x3qb<mode>"
+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1X3B))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (EImode, REGNO (operands[1]) + 6);
+
+ output_asm_insn ("vst1.<V_sz_elem>\t%h1, %A0", ops);
+ return "";
+}
+ [(set_attr "type" "neon_store1_3reg<q>")]
+)
+
(define_insn "neon_vst1_x4<mode>"
[(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 4753968d52f..573bdf00944 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -463,6 +463,8 @@
UNSPEC_VRSRA_U_N
UNSPEC_VSRI
UNSPEC_VST1
+ UNSPEC_VST1X3A
+ UNSPEC_VST1X3B
UNSPEC_VST1_LANE
UNSPEC_VST2
UNSPEC_VST2_LANE
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
index 232feafade0..e9b7d67f06a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
@@ -61,10 +61,70 @@ void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val)
vst1q_p16_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+void test_vst1q_u8_x3 (uint8_t * ptr, uint8x16x3_t val)
+{
+ vst1q_u8_x3 (ptr, val);
+}
+
+void test_vst1q_u16_x3 (uint16_t * ptr, uint16x8x3_t val)
+{
+ vst1q_u16_x3 (ptr, val);
+}
+
+void test_vst1q_u32_x3 (uint32_t * ptr, uint32x4x3_t val)
+{
+ vst1q_u32_x3 (ptr, val);
+}
+
+void test_vst1q_u64_x3 (uint64_t * ptr, uint64x2x3_t val)
+{
+ vst1q_u64_x3 (ptr, val);
+}
+
+void test_vst1q_s8_x3 (int8_t * ptr, int8x16x3_t val)
+{
+ vst1q_s8_x3 (ptr, val);
+}
+
+void test_vst1q_s16_x3 (int16_t * ptr, int16x8x3_t val)
+{
+ vst1q_s16_x3 (ptr, val);
+}
+
+void test_vst1q_s32_x3 (int32_t * ptr, int32x4x3_t val)
+{
+ vst1q_s32_x3 (ptr, val);
+}
+
+void test_vst1q_s64_x3 (int64_t * ptr, int64x2x3_t val)
+{
+ vst1q_s64_x3 (ptr, val);
+}
+
+void test_vst1q_f32_x3 (float32_t * ptr, float32x4x3_t val)
+{
+ vst1q_f32_x3 (ptr, val);
+}
+
+void test_vst1q_p8_x3 (poly8_t * ptr, poly8x16x3_t val)
+{
+ vst1q_p8_x3 (ptr, val);
+}
+
+void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val)
+{
+ vst1q_p16_x3 (ptr, val);
+}
+
+
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
index 2a4579f0aae..44d69522dff 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
@@ -10,4 +10,10 @@ void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val)
vst1q_bf16_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val)
+{
+ vst1q_bf16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
index 61a7e558c48..f0ac2d35c1c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
@@ -10,4 +10,10 @@ void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val)
vst1q_f16_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val)
+{
+ vst1q_f16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
index 82f3dad293c..24fdf3c0c1b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
@@ -10,4 +10,10 @@ void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val)
vst1q_p64_x2 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
+void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val)
+{
+ vst1q_p64_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 1 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 09/12] [GCC] arm: vst1q_types_x4 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (7 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 08/12] [GCC] arm: vst1q_types_x3 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 10/12] [GCC] arm: vld1_types_x2 " Ezra.Sitorus
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vst1q intrinsic for the arm port. This patch adds the
_x4 variants of the vst1q intrinsic.
ACLE:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
(vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
(vst1q_f16_x4, vst1q_f32_x4): New.
(vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
(vst1q_bf16_x4): New.
* config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
* config/arm/neon.md
(neon_vst1q_x4<mode>): New.
(neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
* config/arm/unspecs.md
(UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1q_base_xN_1.c: Updated
* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Updated
* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Updated
* gcc.target/arm/simd/vst1q_p64_xN_1.c: Updated
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 47 ++++++++
gcc/config/arm/unspecs.md | 2 +
.../gcc.target/arm/simd/vst1q_base_xN_1.c | 71 +++++++++--
.../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 9 +-
.../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 9 +-
.../gcc.target/arm/simd/vst1q_p64_xN_1.c | 17 ++-
8 files changed, 252 insertions(+), 18 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 5cec7dd876f..af1f747f262 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11391,6 +11391,38 @@ vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x4 (int8_t * __a, int8x16x4_t __b)
+{
+ union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x4 (int16_t * __a, int16x8x4_t __b)
+{
+ union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x4 (int32_t * __a, int32x4x4_t __b)
+{
+ union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x4 (int64_t * __a, int64x2x4_t __b)
+{
+ union { int64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
@@ -11736,6 +11768,14 @@ vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x4 (poly64_t * __a, poly64x2x4_t __b)
+{
+ union { poly64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11817,6 +11857,24 @@ vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b)
__builtin_neon_vst1q_x3v4sf (__a, __bu.__o);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x4 (float16_t * __a, float16x8x4_t __b)
+{
+ union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x4 (float32_t * __a, float32x4x4_t __b)
+{
+ union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4sf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_u8 (uint8_t * __a, uint8x16_t __b)
@@ -11909,6 +11967,38 @@ vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x4 (uint8_t * __a, uint8x16x4_t __b)
+{
+ union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x4 (uint16_t * __a, uint16x8x4_t __b)
+{
+ union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x4 (uint32_t * __a, uint32x4x4_t __b)
+{
+ union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x4 (uint64_t * __a, uint64x2x4_t __b)
+{
+ union { uint64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_p8 (poly8_t * __a, poly8x16_t __b)
@@ -11955,6 +12045,22 @@ vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b)
__builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x4 (poly8_t * __a, poly8x16x4_t __b)
+{
+ union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x4 (poly16_t * __a, poly16x8x4_t __b)
+{
+ union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
@@ -20647,6 +20753,14 @@ vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b)
__builtin_neon_vst1q_x3v8bf (__a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_bf16_x4 (bfloat16_t * __a, bfloat16x8x4_t __b)
+{
+ union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8bf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index f8ff87c0c7a..df2ca4d8d2b 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -316,6 +316,7 @@ VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index a311ee0c997..4683d8978f9 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5249,6 +5249,53 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_store1_4reg<q>")]
)
+(define_expand "neon_vst1q_x4<mode>"
+ [(match_operand:XI 0 "neon_struct_operand")
+ (match_operand:XI 1 "s_register_operand")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+{
+ rtx mem = adjust_address (operands[0], OImode, 0);
+ emit_insn (gen_neon_vst1x4qa<mode> (mem, operands[1]));
+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
+ emit_insn (gen_neon_vst1x4qb<mode> (mem, operands[1]));
+ DONE;
+})
+
+(define_insn "neon_vst1x4qa<mode>"
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1X4A))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (OImode, REGNO (operands[1]));
+
+ output_asm_insn ("vst1.<V_sz_elem>\t%h1, %A0", ops);
+ return "";
+}
+ [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
+(define_insn "neon_vst1x4qb<mode>"
+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+ (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1X4B))]
+ "TARGET_NEON"
+{
+ rtx ops[2];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (OImode, REGNO (operands[1]) + 8);
+
+ output_asm_insn ("vst1.<V_sz_elem>\t%h1, %A0", ops);
+ return "";
+}
+ [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
;; see comment on neon_vld1_lane for reason why the lane numbers are reversed
;; here on big endian targets.
(define_insn "neon_vst1_lane<mode>"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 573bdf00944..df5f3290fb0 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -465,6 +465,8 @@
UNSPEC_VST1
UNSPEC_VST1X3A
UNSPEC_VST1X3B
+ UNSPEC_VST1X4A
+ UNSPEC_VST1X4B
UNSPEC_VST1_LANE
UNSPEC_VST2
UNSPEC_VST2_LANE
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
index e9b7d67f06a..0700058d3bd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
@@ -116,15 +116,70 @@ void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val)
vst1q_p16_x3 (ptr, val);
}
+void test_vst1q_u8_x4 (uint8_t * ptr, uint8x16x4_t val)
+{
+ vst1q_u8_x4 (ptr, val);
+}
+
+void test_vst1q_u16_x4 (uint16_t * ptr, uint16x8x4_t val)
+{
+ vst1q_u16_x4 (ptr, val);
+}
+
+void test_vst1q_u32_x4 (uint32_t * ptr, uint32x4x4_t val)
+{
+ vst1q_u32_x4 (ptr, val);
+}
+
+void test_vst1q_u64_x4 (uint64_t * ptr, uint64x2x4_t val)
+{
+ vst1q_u64_x4 (ptr, val);
+}
+
+void test_vst1q_s8_x4 (int8_t * ptr, int8x16x4_t val)
+{
+ vst1q_s8_x4 (ptr, val);
+}
+
+void test_vst1q_s16_x4 (int16_t * ptr, int16x8x4_t val)
+{
+ vst1q_s16_x4 (ptr, val);
+}
+
+void test_vst1q_s32_x4 (int32_t * ptr, int32x4x4_t val)
+{
+ vst1q_s32_x4 (ptr, val);
+}
+
+void test_vst1q_s64_x4 (int64_t * ptr, int64x2x4_t val)
+{
+ vst1q_s64_x4 (ptr, val);
+}
+
+void test_vst1q_f32_x4 (float32_t * ptr, float32x4x4_t val)
+{
+ vst1q_f32_x4 (ptr, val);
+}
+
+void test_vst1q_p8_x4 (poly8_t * ptr, poly8x16x4_t val)
+{
+ vst1q_p8_x4 (ptr, val);
+}
+
+void test_vst1q_p16_x4 (poly16_t * ptr, poly16x8x4_t val)
+{
+ vst1q_p16_x4 (ptr, val);
+}
+
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
index 44d69522dff..435f376b587 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
@@ -15,5 +15,10 @@ void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val)
vst1q_bf16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
\ No newline at end of file
+void test_vst1q_bf16_x4 (bfloat16_t * ptr, bfloat16x8x4_t val)
+{
+ vst1q_bf16_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
index f0ac2d35c1c..b26068376be 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
@@ -15,5 +15,10 @@ void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val)
vst1q_f16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 1 } } */
+void test_vst1q_f16_x4 (float16_t * ptr, float16x8x4_t val)
+{
+ vst1q_f16_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]!\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
index 24fdf3c0c1b..f14b4fb6ae6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
@@ -5,15 +5,20 @@
#include "arm_neon.h"
-void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val)
+void test_vst1q_p64_x2(poly64_t *ptr, poly64x2x2_t val)
{
- vst1q_p64_x2 (ptr, val);
+ vst1q_p64_x2(ptr, val);
}
-void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val)
+void test_vst1q_p64_x3(poly64_t *ptr, poly64x2x3_t val)
{
- vst1q_p64_x3 (ptr, val);
+ vst1q_p64_x3(ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 1 } } */
+void test_vst1q_p64_x4(poly64_t *ptr, poly64x2x4_t val)
+{
+ vst1q_p64_x4(ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]!\n} 2 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 10/12] [GCC] arm: vld1_types_x2 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (8 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 09/12] [GCC] arm: vst1q_types_x4 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 11/12] [GCC] arm: vld1_types_x3 " Ezra.Sitorus
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1 intrinsic for the arm port. This patch adds the
_x2 variants of the vld1 intrinsic.
The previous vld1_x2 has been updated to vld1q_x2 to take into
account that it works with 4-word-length types. vld1_x2 is now
only for 2-word-length types.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
(vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
(vld1_f16_x2, vld1_f32_x2): New.
(vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
(vld1_bf16_x2): New.
(vld1q_types_x2): Updated to use vld1q_x2 from
arm_neon_builtins.def
* config/arm/arm_neon_builtins.def
(vld1_x2): Updated entries.
(vld1q_x2): New entries, but comes from the old vld1_x2
* config/arm/neon.md
(neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
neon_vld1_x2<mode>.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 156 ++++++++++++++++--
gcc/config/arm/arm_neon_builtins.def | 7 +-
gcc/config/arm/neon.md | 10 +-
.../gcc.target/arm/simd/vld1_base_xN_1.c | 66 ++++++++
.../gcc.target/arm/simd/vld1_bf16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vld1_fp16_xN_1.c | 13 ++
.../gcc.target/arm/simd/vld1_p64_xN_1.c | 13 ++
7 files changed, 256 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index af1f747f262..669b8fffb40 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10307,6 +10307,15 @@ vld1_p64 (const poly64_t * __a)
return (poly64x1_t) { *__a };
}
+__extension__ extern __inline poly64x1x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p64_x2 (const poly64_t * __a)
+{
+ union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10336,6 +10345,42 @@ vld1_s64 (const int64_t * __a)
return (int64x1_t) { *__a };
}
+__extension__ extern __inline int8x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s8_x2 (const int8_t * __a)
+{
+ union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s16_x2 (const int16_t * __a)
+{
+ union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s32_x2 (const int32_t * __a)
+{
+ union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x1x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s64_x2 (const int64_t * __a)
+{
+ union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10352,6 +10397,26 @@ vld1_f32 (const float32_t * __a)
return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f16_x2 (const float16_t * __a)
+{
+ union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f32_x2 (const float32_t * __a)
+{
+ union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_u8 (const uint8_t * __a)
@@ -10380,6 +10445,42 @@ vld1_u64 (const uint64_t * __a)
return (uint64x1_t) { *__a };
}
+__extension__ extern __inline uint8x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u8_x2 (const uint8_t * __a)
+{
+ union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u16_x2 (const uint16_t * __a)
+{
+ union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x2x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u32_x2 (const uint32_t * __a)
+{
+ union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x1x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u64_x2 (const uint64_t * __a)
+{
+ union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_p8 (const poly8_t * __a)
@@ -10394,6 +10495,24 @@ vld1_p16 (const poly16_t * __a)
return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
}
+__extension__ extern __inline poly8x8x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p8_x2 (const poly8_t * __a)
+{
+ union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p16_x2 (const poly16_t * __a)
+{
+ union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline poly64x2_t
@@ -10408,7 +10527,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p64_x2 (const poly64_t * __a)
{
union { poly64x2x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10464,7 +10583,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s8_x2 (const int8_t * __a)
{
union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10473,7 +10592,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s16_x2 (const int16_t * __a)
{
union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -10482,7 +10601,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s32_x2 (const int32_t * __a)
{
union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -10491,7 +10610,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s64_x2 (const int64_t * __a)
{
union { int64x2x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10589,7 +10708,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f16_x2 (const float16_t * __a)
{
union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v8hf (__a);
+ __rv.__o = __builtin_neon_vld1q_x2v8hf (__a);
return __rv.__i;
}
#endif
@@ -10599,7 +10718,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f32_x2 (const float32_t * __a)
{
union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v4sf ((const __builtin_neon_sf *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v4sf ((const __builtin_neon_sf *) __a);
return __rv.__i;
}
@@ -10676,7 +10795,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8_x2 (const uint8_t * __a)
{
union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10685,7 +10804,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u16_x2 (const uint16_t * __a)
{
union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -10694,7 +10813,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u32_x2 (const uint32_t * __a)
{
union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -10703,7 +10822,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u64_x2 (const uint64_t * __a)
{
union { uint64x2x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10798,7 +10917,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8_x2 (const poly8_t * __a)
{
union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10807,7 +10926,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p16_x2 (const poly16_t * __a)
{
union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -20816,6 +20935,15 @@ vld1_bf16 (bfloat16_t const * __ptr)
return __builtin_neon_vld1v4bf (__ptr);
}
+__extension__ extern __inline bfloat16x4x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_bf16_x2 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x2v4bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16 (const bfloat16_t * __ptr)
@@ -20828,7 +20956,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16_x2 (const bfloat16_t * __ptr)
{
union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x2v8bf ((const __builtin_neon_bf *) __ptr);
+ __rv.__o = __builtin_neon_vld1q_x2v8bf ((const __builtin_neon_bf *) __ptr);
return __rv.__i;
}
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index df2ca4d8d2b..07750c03c08 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -298,12 +298,13 @@ VAR1 (TERNOP, vtbx1, v8qi)
VAR1 (TERNOP, vtbx2, v8qi)
VAR1 (TERNOP, vtbx3, v8qi)
VAR1 (TERNOP, vtbx4, v8qi)
-VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
-VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
-VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR13 (LOAD1, vld1,
v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
+VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR12 (LOAD1LANE, vld1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
VAR10 (LOAD1, vld1_dup,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 4683d8978f9..9f6133a1055 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4957,11 +4957,11 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_1reg<q>")]
)
-(define_insn "neon_vld1_x2<mode>"
- [(set (match_operand:OI 0 "s_register_operand" "=w")
- (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
- (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
- UNSPEC_VLD1))]
+(define_insn "neon_vld1<VMEMX2_q>_x2<VDQX:mode>"
+ [(set (match_operand:VMEMX2 0 "s_register_operand" "=w")
+ (unspec:VMEMX2 [(match_operand:VMEMX2 1 "neon_struct_operand" "Um")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1))]
"TARGET_NEON"
"vld1.<V_sz_elem>\t%h0, %A1"
[(set_attr "type" "neon_load1_2reg<q>")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
new file mode 100644
index 00000000000..6b0e78d94d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
@@ -0,0 +1,66 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x8x2_t test_vld1_u8_x2 (uint8_t * a)
+{
+ return vld1_u8_x2 (a);
+}
+
+uint16x4x2_t test_vld1_u16_x2 (uint16_t * a)
+{
+ return vld1_u16_x2 (a);
+}
+
+uint32x2x2_t test_vld1_u32_x2 (uint32_t * a)
+{
+ return vld1_u32_x2 (a);
+}
+
+uint64x1x2_t test_vld1_u64_x2 (uint64_t * a)
+{
+ return vld1_u64_x2 (a);
+}
+
+int8x8x2_t test_vld1_s8_x2 (int8_t * a)
+{
+ return vld1_s8_x2 (a);
+}
+
+int16x4x2_t test_vld1_s16_x2 (int16_t * a)
+{
+ return vld1_s16_x2 (a);
+}
+
+int32x2x2_t test_vld1_s32_x2 (int32_t * a)
+{
+ return vld1_s32_x2 (a);
+}
+
+int64x1x2_t test_vld1_s64_x2 (int64_t * a)
+{
+ return vld1_s64_x2 (a);
+}
+
+float32x2x2_t test_vld1_f32_x2 (float32_t * a)
+{
+ return vld1_f32_x2 (a);
+}
+
+poly8x8x2_t test_vld1_p8_x2 (poly8_t * a)
+{
+ return vld1_p8_x2 (a);
+}
+
+poly16x4x2_t test_vld1_p16_x2 (poly16_t * a)
+{
+ return vld1_p16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
new file mode 100644
index 00000000000..3ec7a5e1986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a)
+{
+ return vld1_bf16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
new file mode 100644
index 00000000000..c0e5ea49142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+float16x4x2_t test_vld1_f16_x2 (float16_t * a)
+{
+ return vld1_f16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
new file mode 100644
index 00000000000..3ccea520ddc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly64x1x2_t test_vld1_p64_x2 (poly64_t * a)
+{
+ return vld1_p64_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 11/12] [GCC] arm: vld1_types_x3 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (9 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 10/12] [GCC] arm: vld1_types_x2 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 12/12] [GCC] arm: vld1_types_x4 " Ezra.Sitorus
2024-01-12 17:03 ` [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Richard Earnshaw (lists)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1 intrinsic for the arm port. This patch adds the
_x3 variants of the vld1 intrinsic.
The previous vld1_x3 has been updated to vld1q_x3 to take into
account that it works with 4-word-length types. vld1_x3 is now
only for 2-word-length types.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
(vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
(vld1_f16_x3, vld1_f32_x3): New.
(vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
(vld1_bf16_x3): New.
(vld1q_types_x3): Updated to use vld1q_x3 from
arm_neon_builtins.def
* config/arm/arm_neon_builtins.def
(vld1_x3): Updated entries.
(vld1q_x3): New entries, but comes from the old vld1_x2
* config/arm/neon.md
(neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1_base_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_bf16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_fp16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_p64_xN_1.c: Updated.
---
gcc/config/arm/arm_neon.h | 156 ++++++++++++++++--
gcc/config/arm/arm_neon_builtins.def | 3 +-
gcc/config/arm/neon.md | 12 +-
.../gcc.target/arm/simd/vld1_base_xN_1.c | 63 ++++++-
.../gcc.target/arm/simd/vld1_bf16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vld1_fp16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vld1_p64_xN_1.c | 7 +-
7 files changed, 232 insertions(+), 23 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 669b8fffb40..dbc37cafe28 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10316,6 +10316,15 @@ vld1_p64_x2 (const poly64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p64_x3 (const poly64_t * __a)
+{
+ union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10381,6 +10390,42 @@ vld1_s64_x2 (const int64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline int8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s8_x3 (const int8_t * __a)
+{
+ union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s16_x3 (const int16_t * __a)
+{
+ union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s32_x3 (const int32_t * __a)
+{
+ union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s64_x3 (const int64_t * __a)
+{
+ union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10417,6 +10462,26 @@ vld1_f32_x2 (const float32_t * __a)
return __rv.__i;
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f16_x3 (const float16_t * __a)
+{
+ union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f32_x3 (const float32_t * __a)
+{
+ union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_u8 (const uint8_t * __a)
@@ -10481,6 +10546,42 @@ vld1_u64_x2 (const uint64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline uint8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u8_x3 (const uint8_t * __a)
+{
+ union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u16_x3 (const uint16_t * __a)
+{
+ union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u32_x3 (const uint32_t * __a)
+{
+ union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u64_x3 (const uint64_t * __a)
+{
+ union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_p8 (const poly8_t * __a)
@@ -10513,6 +10614,24 @@ vld1_p16_x2 (const poly16_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p8_x3 (const poly8_t * __a)
+{
+ union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p16_x3 (const poly16_t * __a)
+{
+ union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline poly64x2_t
@@ -10536,7 +10655,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p64_x3 (const poly64_t * __a)
{
union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10619,7 +10738,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s8_x3 (const uint8_t * __a)
{
union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10628,7 +10747,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s16_x3 (const uint16_t * __a)
{
union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -10637,7 +10756,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s32_x3 (const int32_t * __a)
{
union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -10646,7 +10765,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s64_x3 (const int64_t * __a)
{
union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10728,7 +10847,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f16_x3 (const float16_t * __a)
{
union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v8hf (__a);
+ __rv.__o = __builtin_neon_vld1q_x3v8hf (__a);
return __rv.__i;
}
#endif
@@ -10738,7 +10857,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f32_x3 (const float32_t * __a)
{
union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v4sf ((const __builtin_neon_sf *) __a);
return __rv.__i;
}
@@ -10831,7 +10950,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8_x3 (const uint8_t * __a)
{
union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10840,7 +10959,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u16_x3 (const uint16_t * __a)
{
union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -10849,7 +10968,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u32_x3 (const uint32_t * __a)
{
union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -10858,7 +10977,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u64_x3 (const uint64_t * __a)
{
union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10935,7 +11054,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8_x3 (const poly8_t * __a)
{
union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10944,7 +11063,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p16_x3 (const poly16_t * __a)
{
union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -20944,6 +21063,15 @@ vld1_bf16_x2 (const bfloat16_t * __ptr)
return __rv.__i;
}
+__extension__ extern __inline bfloat16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_bf16_x3 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x3v4bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16 (const bfloat16_t * __ptr)
@@ -20965,7 +21093,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16_x3 (const bfloat16_t * __ptr)
{
union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr);
+ __rv.__o = __builtin_neon_vld1q_x3v8bf ((const __builtin_neon_bf *) __ptr);
return __rv.__i;
}
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 07750c03c08..c74f0db645b 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -303,7 +303,8 @@ VAR13 (LOAD1, vld1,
v4bf, v8bf)
VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
-VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (LOAD1, vld1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR12 (LOAD1LANE, vld1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 9f6133a1055..411270d7cc6 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4967,7 +4967,17 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_2reg<q>")]
)
-(define_expand "neon_vld1_x3<mode>"
+(define_insn "neon_vld1_x3<mode>"
+ [(set (match_operand:EI 0 "s_register_operand" "=w")
+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1))]
+ "TARGET_NEON"
+ "vld1.<V_sz_elem>\t%h0, %A1"
+ [(set_attr "type" "neon_load1_3reg<q>")]
+)
+
+(define_expand "neon_vld1q_x3<mode>"
[(match_operand:CI 0 "s_register_operand")
(match_operand:CI 1 "neon_struct_operand")
(unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
index 6b0e78d94d7..95314bbe0de 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
@@ -60,7 +60,62 @@ poly16x4x2_t test_vld1_p16_x2 (poly16_t * a)
return vld1_p16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
\ No newline at end of file
+uint8x8x3_t test_vld1_u8_x3 (uint8_t * a)
+{
+ return vld1_u8_x3 (a);
+}
+
+uint16x4x3_t test_vld1_u16_x3 (uint16_t * a)
+{
+ return vld1_u16_x3 (a);
+}
+
+uint32x2x3_t test_vld1_u32_x3 (uint32_t * a)
+{
+ return vld1_u32_x3 (a);
+}
+
+uint64x1x3_t test_vld1_u64_x3 (uint64_t * a)
+{
+ return vld1_u64_x3 (a);
+}
+
+int8x8x3_t test_vld1_s8_x3 (int8_t * a)
+{
+ return vld1_s8_x3 (a);
+}
+
+int16x4x3_t test_vld1_s16_x3 (int16_t * a)
+{
+ return vld1_s16_x3 (a);
+}
+
+int32x2x3_t test_vld1_s32_x3 (int32_t * a)
+{
+ return vld1_s32_x3 (a);
+}
+
+int64x1x3_t test_vld1_s64_x3 (int64_t * a)
+{
+ return vld1_s64_x3 (a);
+}
+
+float32x2x3_t test_vld1_f32_x3 (float32_t * a)
+{
+ return vld1_f32_x3 (a);
+}
+
+poly8x8x3_t test_vld1_p8_x3 (poly8_t * a)
+{
+ return vld1_p8_x3 (a);
+}
+
+poly16x4x3_t test_vld1_p16_x3 (poly16_t * a)
+{
+ return vld1_p16_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
index 3ec7a5e1986..c1935da0a4c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
@@ -10,4 +10,9 @@ bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a)
return vld1_bf16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
\ No newline at end of file
+bfloat16x4x3_t test_vld1_bf16_x3 (bfloat16_t * a)
+{
+ return vld1_bf16_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
index c0e5ea49142..20363239f5b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
@@ -10,4 +10,9 @@ float16x4x2_t test_vld1_f16_x2 (float16_t * a)
return vld1_f16_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
+float16x4x3_t test_vld1_f16_x3 (float16_t * a)
+{
+ return vld1_f16_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
index 3ccea520ddc..210de511c71 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
@@ -10,4 +10,9 @@ poly64x1x2_t test_vld1_p64_x2 (poly64_t * a)
return vld1_p64_x2 (a);
}
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
+poly64x1x3_t test_vld1_p64_x3 (poly64_t * a)
+{
+ return vld1_p64_x3 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 12/12] [GCC] arm: vld1_types_x4 ACLE intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (10 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 11/12] [GCC] arm: vld1_types_x3 " Ezra.Sitorus
@ 2024-01-02 9:23 ` Ezra.Sitorus
2024-01-12 17:03 ` [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Richard Earnshaw (lists)
12 siblings, 0 replies; 14+ messages in thread
From: Ezra.Sitorus @ 2024-01-02 9:23 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw
From: Ezra Sitorus <ezra.sitorus@arm.com>
This patch is part of a series of patches implementing the _xN
variants of the vld1 intrinsic for the arm port. This patch adds the
_x4 variants of the vld1 intrinsic.
The previous vld1_x4 has been updated to vld1q_x4 to take into
account that it works with 4-word-length types. vld1_x4 is now
only for 2-word-length types.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
(vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
(vld1_f16_x4, vld1_f32_x4): New.
(vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
(vld1_bf16_x4): New.
(vld1q_types_x4): Updated to use vld1q_x4
from arm_neon_builtins.def
* config/arm/arm_neon_builtins.def
(vld1_x4): Updated entries.
(vld1q_x4): New entries, but comes from the old vld1_x4
* config/arm/neon.md
(neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1_base_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_bf16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_fp16_xN_1.c: Updated.
* gcc.target/arm/simd/vld1_p64_xN_1.c: Updated.
---
gcc/config/arm/arm_neon.h | 156 ++++++++++++++++--
gcc/config/arm/arm_neon_builtins.def | 3 +-
gcc/config/arm/neon.md | 11 +-
.../gcc.target/arm/simd/vld1_base_xN_1.c | 63 ++++++-
.../gcc.target/arm/simd/vld1_bf16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vld1_fp16_xN_1.c | 7 +-
.../gcc.target/arm/simd/vld1_p64_xN_1.c | 7 +-
7 files changed, 231 insertions(+), 23 deletions(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index dbc37cafe28..8bcf1d6325e 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10325,6 +10325,15 @@ vld1_p64_x3 (const poly64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p64_x4 (const poly64_t * __a)
+{
+ union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#pragma GCC pop_options
__extension__ extern __inline int8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10426,6 +10435,42 @@ vld1_s64_x3 (const int64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline int8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s8_x4 (const int8_t * __a)
+{
+ union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s16_x4 (const int16_t * __a)
+{
+ union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s32_x4 (const int32_t * __a)
+{
+ union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline int64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s64_x4 (const int64_t * __a)
+{
+ union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
__extension__ extern __inline float16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -10482,6 +10527,26 @@ vld1_f32_x3 (const float32_t * __a)
return __rv.__i;
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline float16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f16_x4 (const float16_t * __a)
+{
+ union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4hf (__a);
+ return __rv.__i;
+}
+#endif
+
+__extension__ extern __inline float32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f32_x4 (const float32_t * __a)
+{
+ union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2sf ((const __builtin_neon_sf *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline uint8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_u8 (const uint8_t * __a)
@@ -10582,6 +10647,42 @@ vld1_u64_x3 (const uint64_t * __a)
return __rv.__i;
}
+__extension__ extern __inline uint8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u8_x4 (const uint8_t * __a)
+{
+ union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u16_x4 (const uint16_t * __a)
+{
+ union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u32_x4 (const uint32_t * __a)
+{
+ union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v2si ((const __builtin_neon_si *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline uint64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u64_x4 (const uint64_t * __a)
+{
+ union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4di ((const __builtin_neon_di *) __a);
+ return __rv.__i;
+}
+
__extension__ extern __inline poly8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1_p8 (const poly8_t * __a)
@@ -10632,6 +10733,24 @@ vld1_p16_x3 (const poly16_t * __a)
return __rv.__i;
}
+__extension__ extern __inline poly8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p8_x4 (const poly8_t * __a)
+{
+ union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v8qi ((const __builtin_neon_qi *) __a);
+ return __rv.__i;
+}
+
+__extension__ extern __inline poly16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p16_x4 (const poly16_t * __a)
+{
+ union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4hi ((const __builtin_neon_hi *) __a);
+ return __rv.__i;
+}
+
#pragma GCC push_options
#pragma GCC target ("fpu=crypto-neon-fp-armv8")
__extension__ extern __inline poly64x2_t
@@ -10664,7 +10783,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p64_x4 (const poly64_t * __a)
{
union { poly64x2x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10774,7 +10893,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s8_x4 (const uint8_t * __a)
{
union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10783,7 +10902,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s16_x4 (const uint16_t * __a)
{
union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -10792,7 +10911,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s32_x4 (const int32_t * __a)
{
union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -10801,7 +10920,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_s64_x4 (const int64_t * __a)
{
union { int64x2x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -10867,7 +10986,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f16_x4 (const float16_t * __a)
{
union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v8hf (__a);
+ __rv.__o = __builtin_neon_vld1q_x4v8hf (__a);
return __rv.__i;
}
#endif
@@ -10877,7 +10996,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_f32_x4 (const float32_t * __a)
{
union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v4sf ((const __builtin_neon_sf *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v4sf ((const __builtin_neon_sf *) __a);
return __rv.__i;
}
@@ -10986,7 +11105,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u8_x4 (const uint8_t * __a)
{
union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -10995,7 +11114,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u16_x4 (const uint16_t * __a)
{
union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -11004,7 +11123,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u32_x4 (const uint32_t * __a)
{
union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v4si ((const __builtin_neon_si *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v4si ((const __builtin_neon_si *) __a);
return __rv.__i;
}
@@ -11013,7 +11132,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_u64_x4 (const uint64_t * __a)
{
union { uint64x2x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v2di ((const __builtin_neon_di *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v2di ((const __builtin_neon_di *) __a);
return __rv.__i;
}
@@ -11072,7 +11191,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p8_x4 (const poly8_t * __a)
{
union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v16qi ((const __builtin_neon_qi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a);
return __rv.__i;
}
@@ -11081,7 +11200,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_p16_x4 (const poly16_t * __a)
{
union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v8hi ((const __builtin_neon_hi *) __a);
+ __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a);
return __rv.__i;
}
@@ -21072,6 +21191,15 @@ vld1_bf16_x3 (const bfloat16_t * __ptr)
return __rv.__i;
}
+__extension__ extern __inline bfloat16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_bf16_x4 (const bfloat16_t * __ptr)
+{
+ union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+ __rv.__o = __builtin_neon_vld1_x4v4bf ((const __builtin_neon_bf *) __ptr);
+ return __rv.__i;
+}
+
__extension__ extern __inline bfloat16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16 (const bfloat16_t * __ptr)
@@ -21102,7 +21230,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vld1q_bf16_x4 (const bfloat16_t * __ptr)
{
union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__o = __builtin_neon_vld1_x4v8bf ((const __builtin_neon_bf *) __ptr);
+ __rv.__o = __builtin_neon_vld1q_x4v8bf ((const __builtin_neon_bf *) __ptr);
return __rv.__i;
}
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index c74f0db645b..20dfcae7de5 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -305,7 +305,8 @@ VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (LOAD1, vld1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (LOAD1, vld1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
-VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
+VAR7 (LOAD1, vld1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (LOAD1, vld1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR12 (LOAD1LANE, vld1_lane,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf)
VAR10 (LOAD1, vld1_dup,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 411270d7cc6..5ad769484bc 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5025,7 +5025,16 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_load1_3reg<q>")]
)
-(define_expand "neon_vld1_x4<mode>"
+(define_insn "neon_vld1_x4<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD1))]
+ "TARGET_NEON"
+ "vld1.<V_sz_elem>\t%h0, %A1"
+ [(set_attr "type" "neon_load1_4reg<q>")]
+)
+(define_expand "neon_vld1q_x4<mode>"
[(match_operand:XI 0 "s_register_operand")
(match_operand:XI 1 "neon_struct_operand")
(unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
index 95314bbe0de..a5686ffac01 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
@@ -115,7 +115,62 @@ poly16x4x3_t test_vld1_p16_x3 (poly16_t * a)
return vld1_p16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
\ No newline at end of file
+uint8x8x4_t test_vld1_u8_x4 (uint8_t * a)
+{
+ return vld1_u8_x4 (a);
+}
+
+uint16x4x4_t test_vld1_u16_x4 (uint16_t * a)
+{
+ return vld1_u16_x4 (a);
+}
+
+uint32x2x4_t test_vld1_u32_x4 (uint32_t * a)
+{
+ return vld1_u32_x4 (a);
+}
+
+uint64x1x4_t test_vld1_u64_x4 (uint64_t * a)
+{
+ return vld1_u64_x4 (a);
+}
+
+int8x8x4_t test_vld1_s8_x4 (int8_t * a)
+{
+ return vld1_s8_x4 (a);
+}
+
+int16x4x4_t test_vld1_s16_x4 (int16_t * a)
+{
+ return vld1_s16_x4 (a);
+}
+
+int32x2x4_t test_vld1_s32_x4 (int32_t * a)
+{
+ return vld1_s32_x4 (a);
+}
+
+int64x1x4_t test_vld1_s64_x4 (int64_t * a)
+{
+ return vld1_s64_x4 (a);
+}
+
+float32x2x4_t test_vld1_f32_x4 (float32_t * a)
+{
+ return vld1_f32_x4 (a);
+}
+
+poly8x8x4_t test_vld1_p8_x4 (poly8_t * a)
+{
+ return vld1_p8_x4 (a);
+}
+
+poly16x4x4_t test_vld1_p16_x4 (poly16_t * a)
+{
+ return vld1_p16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
index c1935da0a4c..7ed17834ccf 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
@@ -15,4 +15,9 @@ bfloat16x4x3_t test_vld1_bf16_x3 (bfloat16_t * a)
return vld1_bf16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
\ No newline at end of file
+bfloat16x4x4_t test_vld1_bf16_x4 (bfloat16_t * a)
+{
+ return vld1_bf16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
index 20363239f5b..82e7211ebbf 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
@@ -15,4 +15,9 @@ float16x4x3_t test_vld1_f16_x3 (float16_t * a)
return vld1_f16_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+float16x4x4_t test_vld1_f16_x4 (float16_t * a)
+{
+ return vld1_f16_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
index 210de511c71..644371b89ea 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
@@ -15,4 +15,9 @@ poly64x1x3_t test_vld1_p64_x3 (poly64_t * a)
return vld1_p64_x3 (a);
}
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
+poly64x1x4_t test_vld1_p64_x4 (poly64_t * a)
+{
+ return vld1_p64_x4 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics
2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
` (11 preceding siblings ...)
2024-01-02 9:23 ` [PATCH v3 12/12] [GCC] arm: vld1_types_x4 " Ezra.Sitorus
@ 2024-01-12 17:03 ` Richard Earnshaw (lists)
12 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw (lists) @ 2024-01-12 17:03 UTC (permalink / raw)
To: Ezra.Sitorus, gcc-patches
On 02/01/2024 09:23, Ezra.Sitorus@arm.com wrote:
> From: Ezra Sitorus <ezra.sitorus@arm.com>
>
> Add vld1q, vst1, vst1q and vst1 intrinsics to arm port.
>
> Ezra Sitorus (12):
> [GCC] arm: vld1q_types_x2 ACLE intrinsics
> [GCC] arm: vld1q_types_x3 ACLE intrinsics
> [GCC] arm: vld1q_types_x4 ACLE intrinsics
> [GCC] arm: vst1_types_x2 ACLE intrinsics
> [GCC] arm: vst1_types_x3 ACLE intrinsics
> [GCC] arm: vst1_types_x4 ACLE intrinsics
> [GCC] arm: vst1q_types_x2 ACLE intrinsics
> [GCC] arm: vst1q_types_x3 ACLE intrinsics
> [GCC] arm: vst1q_types_x4 ACLE intrinsics
> [GCC] arm: vld1_types_x2 ACLE intrinsics
> [GCC] arm: vld1_types_x3 ACLE intrinsics
> [GCC] arm: vld1_types_x4 ACLE intrinsics
>
> gcc/config/arm/arm_neon.h | 2032 ++++++++++++++---
> gcc/config/arm/arm_neon_builtins.def | 12 +
> gcc/config/arm/iterators.md | 6 +
> gcc/config/arm/neon.md | 249 ++
> gcc/config/arm/unspecs.md | 8 +
> .../gcc.target/arm/simd/vld1_base_xN_1.c | 176 ++
> .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 23 +
> .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 23 +
> .../gcc.target/arm/simd/vld1_p64_xN_1.c | 23 +
> .../gcc.target/arm/simd/vld1q_base_xN_1.c | 183 ++
> .../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 24 +
> .../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 24 +
> .../gcc.target/arm/simd/vld1q_p64_xN_1.c | 24 +
> .../gcc.target/arm/simd/vst1_base_xN_1.c | 176 ++
> .../gcc.target/arm/simd/vst1_bf16_xN_1.c | 22 +
> .../gcc.target/arm/simd/vst1_fp16_xN_1.c | 23 +
> .../gcc.target/arm/simd/vst1_p64_xN_1.c | 23 +
> .../gcc.target/arm/simd/vst1q_base_xN_1.c | 185 ++
> .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 24 +
> .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 24 +
> .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 24 +
> 21 files changed, 3018 insertions(+), 290 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
>
Thanks, I've pushed this series.
Reviewing this series did highlight a couple of issues with the existing code base (not your patch); I'll follow up on these separately.
R.
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2024-01-12 17:03 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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2024-01-02 9:23 [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 01/12] [GCC] arm: vld1q_types_x2 ACLE intrinsics Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 02/12] [GCC] arm: vld1q_types_x3 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 03/12] [GCC] arm: vld1q_types_x4 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 04/12] [GCC] arm: vst1_types_x2 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 05/12] [GCC] arm: vst1_types_x3 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 06/12] [GCC] arm: vst1_types_x4 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 07/12] [GCC] arm: vst1q_types_x2 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 08/12] [GCC] arm: vst1q_types_x3 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 09/12] [GCC] arm: vst1q_types_x4 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 10/12] [GCC] arm: vld1_types_x2 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 11/12] [GCC] arm: vld1_types_x3 " Ezra.Sitorus
2024-01-02 9:23 ` [PATCH v3 12/12] [GCC] arm: vld1_types_x4 " Ezra.Sitorus
2024-01-12 17:03 ` [PATCH v3 00/12] [GCC] arm: vld1q vst1 vst1q vst1 intrinsics Richard Earnshaw (lists)
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