[committed] MIPS: define_attr perf_ratio in mips.md

[committed] MIPS: define_attr perf_ratio in mips.md

[YunQiang Su]

The accurate cost of an pattern can get with
	 insn_count * perf_ratio

The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern.  Since it is not set for most
patterns yet, to use it, we will need to be sure that it's
value is greater than 0.

This attr will be used in `mips_insn_cost`.

gcc

	* config/mips/mips.md (perf_ratio): New attribute.
---
 gcc/config/mips/mips.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 6d47241ea3a..e1762ce105b 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -312,6 +312,10 @@ (define_attr "sync_insn2" "nop,and,xor,not"
 ;; "11" specifies MEMMODEL_ACQUIRE.
 (define_attr "sync_memmodel" "" (const_int 10))
 
+;; Performance ratio.  Add this attr to the slow INSNs.
+;; Used by mips_insn_cost.
+(define_attr "perf_ratio" "" (const_int 0))
+
 ;; Accumulator operand for madd patterns.
 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
 
-- 
2.39.2

[committed] MIPS: Implement TARGET_INSN_COSTS

[YunQiang Su]

When combine some instructions, the generic `rtx_cost`
may over estimate the cost of result RTL, due to that
the RTL may be quite complex and `rtx_cost` has no
information that this RTL can be convert to simple
hardware instruction(s).

In this case, Let's use `insn_count * perf_ratio` to
estimate the cost if both of them are available.
Otherwise fallback to pattern_cost.

When non-speed, Let's use the length as cost.

gcc

	* config/mips/mips.cc (mips_insn_cost): New function.

gcc/testsuite

	* gcc.target/mips/data-sym-multi-pool.c: Skip Os or -O0.
---
 gcc/config/mips/mips.cc                       | 33 +++++++++++++++++++
 .../gcc.target/mips/data-sym-multi-pool.c     |  2 +-
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 3131749d6ea..46b7d9b64ff 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -4170,6 +4170,37 @@ mips_set_reg_reg_cost (machine_mode mode)
     }
 }
 
+/* Implement TARGET_INSN_COSTS.  */
+
+static int
+mips_insn_cost (rtx_insn *x, bool speed)
+{
+  int cost;
+  int count;
+  int ratio;
+
+  if (recog_memoized (x) < 0
+      && GET_CODE (PATTERN (x)) != ASM_INPUT
+      && asm_noperands (PATTERN (x)) < 0)
+    goto pattern_cost;
+
+  /* FIXME: return get_attr_length?  More tests may be needed.  */
+  if (!speed)
+    goto pattern_cost;
+
+  count = get_attr_insn_count (x);
+  ratio = get_attr_perf_ratio (x);
+  cost = count * ratio;
+  if (cost > 0)
+    return cost;
+
+pattern_cost:
+  cost = pattern_cost (PATTERN (x), speed);
+  /* If the cost is zero, then it's likely a complex insn.
+     FIXME: Return COSTS_N_INSNS (2)?  More tests are needed.  */
+  return cost;
+}
+
 /* Implement TARGET_RTX_COSTS.  */
 
 static bool
@@ -23069,6 +23100,8 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m)
 #define TARGET_RTX_COSTS mips_rtx_costs
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST mips_address_cost
+#undef  TARGET_INSN_COST
+#define TARGET_INSN_COST mips_insn_cost
 
 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
diff --git a/gcc/testsuite/gcc.target/mips/data-sym-multi-pool.c b/gcc/testsuite/gcc.target/mips/data-sym-multi-pool.c
index 3cf2d4f0248..8643095ff9f 100644
--- a/gcc/testsuite/gcc.target/mips/data-sym-multi-pool.c
+++ b/gcc/testsuite/gcc.target/mips/data-sym-multi-pool.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-mips16 -mcode-readable=yes -fno-tree-vrp -fno-tree-dominator-opts" } */
-/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
+/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" "-O0" "-Os" } { "" } } */
 
 /* This testcase generates multiple constant pools within a function body.  */
 
-- 
2.39.2

[committed] MIPS: Add pattern insqisi_extended and inshisi_extended

[YunQiang Su]

This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.

For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation.  Since 32bit INS instruction can be sure that
result is sign-extended, and the QImode src register is safe for INS, too.

(insn 19 18 20 2 (set (zero_extract:DI (reg/v:DI 200 [ val ])
            (const_int 8 [0x8])
            (const_int 24 [0x18]))
        (subreg:DI (reg:QI 205) 0)) "../xx.c":7:29 -1
     (nil))
(insn 20 19 23 2 (set (reg/v:DI 200 [ val ])
        (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "../xx.c":7:29 -1
     (nil))

Combine try to merge them to:

(insn 20 19 23 2 (set (reg/v:DI 200 [ val ])
        (sign_extend:DI (ior:SI (and:SI (subreg:SI (reg/v:DI 200 [ val ]) 0)
                    (const_int 16777215 [0xffffff]))
                (ashift:SI (subreg:SI (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) 0)
                    (const_int 24 [0x18]))))) "../xx.c":7:29 18 {*insv_extended}
     (expr_list:REG_DEAD (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ])
        (nil)))

And do similarly for 16/16 pair:
(insn 13 12 14 2 (set (zero_extract:DI (reg/v:DI 198 [ val ])
            (const_int 16 [0x10])
            (const_int 16 [0x10]))
        (subreg:DI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0)) "xx.c":5:30 286 {*insvdi}
     (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ])
        (nil)))
(insn 14 13 17 2 (set (reg/v:DI 198 [ val ])
        (sign_extend:DI (subreg:SI (reg/v:DI 198 [ val ]) 0))) "xx.c":5:30 241 {extendsidi2}
     (nil))
------------>
(insn 14 13 17 2 (set (reg/v:DI 198 [ val ])
        (sign_extend:DI (ior:SI (ashift:SI (subreg:SI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0)
                    (const_int 16 [0x10]))
                (zero_extend:SI (subreg:HI (reg/v:DI 198 [ val ]) 0))))) "xx.c":5:30 284 {*inshisi_extended}
     (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ])
        (nil)))

Let's accept these patterns, and set the cost to 1 instruction.

gcc

	PR rtl-optimization/104914
	* config/mips/mips.md (insqisi_extended): New patterns.
	(inshisi_extended): Ditto.

gcc/testsuite

	* gcc.target/mips/pr104914.c: New test.
---
 gcc/config/mips/mips.md                  | 24 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/mips/pr104914.c | 25 ++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr104914.c

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e1762ce105b..17dfcbd6722 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4419,6 +4419,30 @@ (define_insn "*extzv_truncsi_exts"
   [(set_attr "type"     "arith")
    (set_attr "mode"     "SI")])
 
+(define_insn "*insqisi_extended"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+    (sign_extend:DI
+      (ior:SI (and:SI (subreg:SI (match_dup 0) 0)
+		(const_int 16777215))
+	      (ashift:SI
+		(subreg:SI (match_operand:QI 1 "register_operand" "d") 0)
+		(const_int 24)))))]
+  "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXT_INS"
+  "ins\t%0,%1,24,8"
+  [(set_attr "mode" "SI")
+   (set_attr "perf_ratio" "1")])
+
+(define_insn "*inshisi_extended"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+    (sign_extend:DI
+      (ior:SI
+	(ashift:SI (subreg:SI (match_operand:HI 1 "register_operand" "d") 0)
+	  (const_int 16))
+	(zero_extend:SI (subreg:HI (match_dup 0) 0)))))]
+  "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXT_INS"
+  "ins\t%0,%1,16,16"
+  [(set_attr "mode" "SI")
+   (set_attr "perf_ratio" "1")])
 
 (define_expand "insvmisalign<mode>"
   [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
diff --git a/gcc/testsuite/gcc.target/mips/pr104914.c b/gcc/testsuite/gcc.target/mips/pr104914.c
new file mode 100644
index 00000000000..5dd10e84c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr104914.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mabi=64" } */
+
+extern void abort (void);
+extern void exit (int);
+
+NOMIPS16 int test (const unsigned char *buf)
+{
+  int val;
+  ((unsigned char*)&val)[0] = *buf++;
+  ((unsigned char*)&val)[1] = *buf++;
+  ((unsigned char*)&val)[2] = *buf++;
+  ((unsigned char*)&val)[3] = *buf++;
+  if(val > 0)
+    return 1;
+  else
+    return 0;
+}
+
+int main ()
+{
+  if (test("\xff\xff\xff\xff") != 0)
+    abort();
+  exit(0);
+}
-- 
2.39.2

[committed] MIPS/testsuite: Include stdio.h in mipscop tests

[YunQiang Su]

gcc/testsuite

	* gcc.c-torture/compile/mipscop-1.c: Include stdio.h.
	* gcc.c-torture/compile/mipscop-2.c: Ditto.
	* gcc.c-torture/compile/mipscop-3.c: Ditto.
	* gcc.c-torture/compile/mipscop-4.c: Ditto.
---
 gcc/testsuite/gcc.c-torture/compile/mipscop-1.c | 1 +
 gcc/testsuite/gcc.c-torture/compile/mipscop-2.c | 1 +
 gcc/testsuite/gcc.c-torture/compile/mipscop-3.c | 1 +
 gcc/testsuite/gcc.c-torture/compile/mipscop-4.c | 1 +
 4 files changed, 4 insertions(+)

diff --git a/gcc/testsuite/gcc.c-torture/compile/mipscop-1.c b/gcc/testsuite/gcc.c-torture/compile/mipscop-1.c
index 8a40ba1c6b7..2ba0ee79b8b 100644
--- a/gcc/testsuite/gcc.c-torture/compile/mipscop-1.c
+++ b/gcc/testsuite/gcc.c-torture/compile/mipscop-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target mips*-*-* } } */
 
+#include <stdio.h>
 register unsigned int cp0count asm ("$c0r1");
 
 int __attribute__ ((nomips16))
diff --git a/gcc/testsuite/gcc.c-torture/compile/mipscop-2.c b/gcc/testsuite/gcc.c-torture/compile/mipscop-2.c
index 94df41d65f9..6fffc8ec098 100644
--- a/gcc/testsuite/gcc.c-torture/compile/mipscop-2.c
+++ b/gcc/testsuite/gcc.c-torture/compile/mipscop-2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target mips*-*-* } } */
 
+#include <stdio.h>
 register unsigned int c3r1 asm ("$c3r1");
 
 extern unsigned int b, c;
diff --git a/gcc/testsuite/gcc.c-torture/compile/mipscop-3.c b/gcc/testsuite/gcc.c-torture/compile/mipscop-3.c
index cb4bd4d3efb..03e30117bc1 100644
--- a/gcc/testsuite/gcc.c-torture/compile/mipscop-3.c
+++ b/gcc/testsuite/gcc.c-torture/compile/mipscop-3.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target mips*-*-* } } */
 
+#include <stdio.h>
 register unsigned int c3r1 asm ("$c3r1"), c3r2 asm ("$c3r2");
 
 extern unsigned int b, c;
diff --git a/gcc/testsuite/gcc.c-torture/compile/mipscop-4.c b/gcc/testsuite/gcc.c-torture/compile/mipscop-4.c
index 263fc5cacc1..7e000c1c68a 100644
--- a/gcc/testsuite/gcc.c-torture/compile/mipscop-4.c
+++ b/gcc/testsuite/gcc.c-torture/compile/mipscop-4.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target mips*-*-* } } */
 
+#include <stdio.h>
 register unsigned long c3r1 asm ("$c3r1"), c3r2 asm ("$c3r2");
 
 extern unsigned long b, c;
-- 
2.39.2