* [PATCH v2 1/7] LoongArch: testsuite:Added support for vector object detection.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 2/7] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12,23}.c file chenxiaolong
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
In the GCC of LoongArch architecture, the detection function of common
vectorization test cases is enabled. The following detection procedure
is added to the target-supports.exp file:
1.check_effective_target_scalar_all_fma
2.check_effective_target_vect_int
3.check_effective_target_vect_intfloat_cvt
4.check_effective_target_vect_doubleint_cvt
5.check_effective_target_vect_intdouble_cvt
6.check_effective_target_vect_uintfloat_cvt
7.check_effective_target_vect_floatint_cvt
8.check_effective_target_vect_floatuint_cvt
9.check_effective_target_vect_shift
10.check_effective_target_vect_var_shift
11.check_effective_target_whole_vector_shift
12.check_effective_target_vect_bswap
13.check_effective_target_vect_bool_cmp
14.check_effective_target_vect_char_add
15.check_effective_target_vect_shift_char
16.check_effective_target_vect_long
17.check_effective_target_vect_float
18.check_effective_target_vect_double
19.check_effective_target_vect_long_long
20.check_effective_target_vect_perm
21.check_effective_target_vect_perm_byte
22.check_effective_target_vect_perm_short
23.check_effective_target_vect_widen_sum_hi_to_si
24.check_effective_target_vect_widen_sum_qi_to_hi
25.check_effective_target_vect_widen_sum_qi_to_hi
26.check_effective_target_vect_widen_mult_qi_to_hi
27.check_effective_target_vect_widen_mult_hi_to_si
28.check_effective_target_vect_widen_mult_qi_to_hi_pattern
29.check_effective_target_vect_widen_mult_hi_to_si_pattern
30.check_effective_target_vect_widen_mult_si_to_di_pattern
31.check_effective_target_vect_sdot_qi
32.check_effective_target_vect_udot_qi
33.check_effective_target_vect_sdot_hi
34.check_effective_target_vect_udot_hi
35.check_effective_target_vect_usad_char
36.check_effective_target_vect_avg_qi
37.check_effective_target_vect_pack_trunc
38.check_effective_target_vect_unpack
39.check_effective_target_vect_hw_misalign
40.check_effective_target_vect_gather_load_ifn
40.check_effective_target_vect_condition
42.check_effective_target_vect_cond_mixed
43.check_effective_target_vect_char_mult
44.check_effective_target_vect_short_mult
45.check_effective_target_vect_int_mult
46.check_effective_target_vect_long_mult
47.check_effective_target_vect_int_mod
48.check_effective_target_vect_extract_even_odd
49.check_effective_target_vect_interleave
50.check_effective_target_vect_call_copysignf
51.check_effective_target_vect_call_sqrtf
52.check_effective_target_vect_call_lrint
53.check_effective_target_vect_call_btrunc
54.check_effective_target_vect_call_btruncf
55.check_effective_target_vect_call_ceil
56.check_effective_target_vect_call_ceilf
57.check_effective_target_vect_call_floor
58.check_effective_target_vect_call_floorf
59.check_effective_target_vect_call_lceil
60.check_effective_target_vect_call_lfloor
61.check_effective_target_vect_logical_reduc
62.check_effective_target_section_anchors
63.check_vect_support_and_set_flags
64.check_effective_target_vect_max_reduc
65.check_effective_target_loongarch_sx
66.check_effective_target_loongarch_sx_hw
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add LoongArch to the list of supported
targets.
---
gcc/testsuite/lib/target-supports.exp | 217 +++++++++++++++++++-------
1 file changed, 162 insertions(+), 55 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 167e630f5a5..9addf35ade4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3815,7 +3815,11 @@ proc add_options_for_bfloat16 { flags } {
# (fma, fms, fnma, and fnms) for both float and double.
proc check_effective_target_scalar_all_fma { } {
- return [istarget aarch64*-*-*]
+ if { [istarget aarch64*-*-*]
+ || [istarget loongarch*-*-*]} {
+ return 1
+ }
+ return 0
}
# Return 1 if the target supports compiling fixed-point,
@@ -4051,6 +4055,8 @@ proc check_effective_target_vect_int { } {
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
&& [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx])
}}]
}
@@ -4218,7 +4224,9 @@ proc check_effective_target_vect_intfloat_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe2])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports signed double->int conversion
@@ -4239,7 +4247,9 @@ proc check_effective_target_vect_doubleint_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports signed int->double conversion
@@ -4260,7 +4270,9 @@ proc check_effective_target_vect_intdouble_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
#Return 1 if we're supporting __int128 for target, 0 otherwise.
@@ -4293,7 +4305,9 @@ proc check_effective_target_vect_uintfloat_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe2])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
@@ -4312,7 +4326,9 @@ proc check_effective_target_vect_floatint_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe2])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports unsigned float->int conversion
@@ -4329,7 +4345,9 @@ proc check_effective_target_vect_floatuint_cvt { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe2])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector integer char -> long long extend optab
@@ -4338,7 +4356,9 @@ proc check_effective_target_vect_floatuint_cvt { } {
proc check_effective_target_vect_ext_char_longlong { } {
return [check_cached_effective_target_indexed vect_ext_char_longlong {
expr { ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if peeling for alignment might be profitable on the target
@@ -7462,7 +7482,9 @@ proc check_effective_target_vect_shift { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports hardware vector shift by register operation.
@@ -7474,6 +7496,8 @@ proc check_effective_target_vect_var_shift { } {
|| [istarget aarch64*-*-*]
|| ([istarget riscv*-*-*]
&& [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx])
}}]
}
@@ -7490,7 +7514,9 @@ proc check_effective_target_whole_vector_shift { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) } {
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) } {
set answer 1
} else {
set answer 0
@@ -7507,6 +7533,7 @@ proc check_effective_target_vect_bswap { } {
expr { ([istarget aarch64*-*-*]
|| [is-effective-target arm_neon]
|| [istarget amdgcn-*-*])
+ || [istarget loongarch*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
}
@@ -7520,7 +7547,9 @@ proc check_effective_target_vect_bool_cmp { } {
|| [istarget aarch64*-*-*]
|| [is-effective-target arm_neon]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports addition of char vectors for at least
@@ -7543,6 +7572,8 @@ proc check_effective_target_vect_char_add { } {
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
&& [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx])
}}]
}
@@ -7559,7 +7590,9 @@ proc check_effective_target_vect_shift_char { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
@@ -7580,7 +7613,9 @@ proc check_effective_target_vect_long { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) } {
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) } {
set answer 1
} else {
set answer 0
@@ -7610,7 +7645,9 @@ proc check_effective_target_vect_float { } {
&& [check_effective_target_s390_vxe])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports hardware vectors of float without
@@ -7641,7 +7678,9 @@ proc check_effective_target_vect_double { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v])} }]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports conditional addition, subtraction,
@@ -7669,7 +7708,9 @@ proc check_effective_target_vect_long_long { } {
&& [check_effective_target_has_arch_pwr8])
|| [istarget aarch64*-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v])}}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx])}}]
}
@@ -7724,7 +7765,9 @@ proc check_effective_target_vect_perm { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if, for some VF:
@@ -7819,7 +7862,9 @@ proc check_effective_target_vect_perm_byte { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -7850,7 +7895,9 @@ proc check_effective_target_vect_perm_short { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -7898,6 +7945,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } {
expr { [check_effective_target_vect_unpack]
|| [istarget powerpc*-*-*]
|| [istarget ia64-*-*]
+ || [istarget loongarch*-*-*]
|| [istarget riscv*-*-*] }}]
}
@@ -7913,7 +7961,8 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } {
expr { [check_effective_target_vect_unpack]
|| [is-effective-target arm_neon]
|| [istarget ia64-*-*]
- || [istarget riscv*-*-*] }}]
+ || [istarget riscv*-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target plus current options supports a vector
@@ -7924,6 +7973,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } {
proc check_effective_target_vect_widen_sum_qi_to_si { } {
return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
expr { [istarget powerpc*-*-*]
+ || [istarget loongarch*-*-*]
|| [istarget riscv*-*-*] }}]
}
@@ -7944,6 +7994,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } {
|| ([istarget aarch64*-*-*]
&& ![check_effective_target_aarch64_sve])
|| [is-effective-target arm_neon]
+ || [is-effective-target loongarch*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]))
|| [istarget amdgcn-*-*] }}]
@@ -7968,6 +8019,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } {
&& ![check_effective_target_aarch64_sve])
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [is-effective-target arm_neon]
+ || [is-effective-target loongarch*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]))
|| [istarget amdgcn-*-*] }}]
@@ -7985,6 +8037,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
&& [check_effective_target_arm_little_endian])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
+ || [istarget loongarch*-*-*]
|| [istarget amdgcn-*-*] }}]
}
@@ -7997,6 +8050,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern {
expr { [istarget powerpc*-*-*]
|| [istarget ia64-*-*]
+ || [istarget loongarch*-*-*]
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|| ([is-effective-target arm_neon]
&& [check_effective_target_arm_little_endian])
@@ -8014,6 +8068,7 @@ proc check_effective_target_vect_widen_mult_si_to_di_pattern { } {
return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern {
expr { [istarget ia64-*-*]
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
+ || [istarget loongarch*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
}
@@ -8041,7 +8096,9 @@ proc check_effective_target_vect_sdot_qi { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports a vector
@@ -8058,7 +8115,9 @@ proc check_effective_target_vect_udot_qi { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports a vector
@@ -8087,7 +8146,9 @@ proc check_effective_target_vect_sdot_hi { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports a vector
@@ -8101,7 +8162,9 @@ proc check_effective_target_vect_udot_hi { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports a vector
@@ -8118,7 +8181,9 @@ proc check_effective_target_vect_usad_char { } {
|| ([istarget powerpc*-*-*]
&& [check_p9vector_hw_available])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports both signed
@@ -8128,7 +8193,9 @@ proc check_effective_target_vect_avg_qi {} {
return [expr { ([istarget aarch64*-*-*]
&& ![check_effective_target_aarch64_sve1_only])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }]
}
# Return 1 if the target plus current options supports both signed
@@ -8167,7 +8234,9 @@ proc check_effective_target_vect_pack_trunc { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn*-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options supports a vector
@@ -8189,7 +8258,9 @@ proc check_effective_target_vect_unpack { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn*-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target plus current options does not guarantee
@@ -8230,7 +8301,8 @@ proc check_effective_target_vect_hw_misalign { } {
|| ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
- || ([istarget riscv*-*-*]) } {
+ || ([istarget riscv*-*-*])
+ || ([istarget loongarch*-*-*]) } {
return 1
}
if { [istarget arm*-*-*]
@@ -8849,7 +8921,8 @@ proc check_effective_target_vect_gather_load_ifn { } {
proc check_effective_target_vect_scatter_store { } {
return [expr { [check_effective_target_aarch64_sve]
|| [istarget amdgcn*-*-*]
- || [check_effective_target_riscv_v] }]
+ || [check_effective_target_riscv_v]
+ || [check_effective_target_loongarch_sx] }]
}
# Return 1 if the target supports vector conditional operations, 0 otherwise.
@@ -8868,7 +8941,9 @@ proc check_effective_target_vect_condition { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector conditional operations where
@@ -8887,7 +8962,9 @@ proc check_effective_target_vect_cond_mixed { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector char multiplication, 0 otherwise.
@@ -8905,7 +8982,9 @@ proc check_effective_target_vect_char_mult { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector short multiplication, 0 otherwise.
@@ -8924,7 +9003,9 @@ proc check_effective_target_vect_short_mult { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector int multiplication, 0 otherwise.
@@ -8942,7 +9023,9 @@ proc check_effective_target_vect_int_mult { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports 64 bit hardware vector
@@ -8961,7 +9044,9 @@ proc check_effective_target_vect_long_mult { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) } {
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) } {
set answer 1
} else {
set answer 0
@@ -8999,7 +9084,9 @@ proc check_effective_target_vect_extract_even_odd { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector interleaving, 0 otherwise.
@@ -9017,7 +9104,9 @@ proc check_effective_target_vect_interleave { } {
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
foreach N {2 3 4 5 6 7 8} {
@@ -9142,7 +9231,9 @@ proc check_effective_target_vect_call_copysignf { } {
|| [istarget aarch64*-*-*]
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports hardware square root instructions.
@@ -9181,7 +9272,9 @@ proc check_effective_target_vect_call_sqrtf { } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]
|| ([istarget riscv*-*-*]
- && [check_effective_target_riscv_v]) }}]
+ && [check_effective_target_riscv_v])
+ || ([istarget loongarch*-*-*]
+ && [check_effective_target_loongarch_sx]) }}]
}
# Return 1 if the target supports vector lrint calls.
@@ -9190,7 +9283,8 @@ proc check_effective_target_vect_call_lrint { } {
set et_vect_call_lrint 0
if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
&& [check_effective_target_ilp32])
- || [istarget amdgcn-*-*] } {
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] } {
set et_vect_call_lrint 1
}
@@ -9203,7 +9297,8 @@ proc check_effective_target_vect_call_lrint { } {
proc check_effective_target_vect_call_btrunc { } {
return [check_cached_effective_target_indexed vect_call_btrunc {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector btruncf calls.
@@ -9211,7 +9306,8 @@ proc check_effective_target_vect_call_btrunc { } {
proc check_effective_target_vect_call_btruncf { } {
return [check_cached_effective_target_indexed vect_call_btruncf {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector ceil calls.
@@ -9219,7 +9315,8 @@ proc check_effective_target_vect_call_btruncf { } {
proc check_effective_target_vect_call_ceil { } {
return [check_cached_effective_target_indexed vect_call_ceil {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector ceilf calls.
@@ -9227,7 +9324,8 @@ proc check_effective_target_vect_call_ceil { } {
proc check_effective_target_vect_call_ceilf { } {
return [check_cached_effective_target_indexed vect_call_ceilf {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector floor calls.
@@ -9235,7 +9333,8 @@ proc check_effective_target_vect_call_ceilf { } {
proc check_effective_target_vect_call_floor { } {
return [check_cached_effective_target_indexed vect_call_floor {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector floorf calls.
@@ -9243,21 +9342,24 @@ proc check_effective_target_vect_call_floor { } {
proc check_effective_target_vect_call_floorf { } {
return [check_cached_effective_target_indexed vect_call_floorf {
expr { [istarget aarch64*-*-*]
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector lceil calls.
proc check_effective_target_vect_call_lceil { } {
return [check_cached_effective_target_indexed vect_call_lceil {
- expr { [istarget aarch64*-*-*] }}]
+ expr { [istarget aarch64*-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector lfloor calls.
proc check_effective_target_vect_call_lfloor { } {
return [check_cached_effective_target_indexed vect_call_lfloor {
- expr { [istarget aarch64*-*-*] }}]
+ expr { [istarget aarch64*-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports vector nearbyint calls.
@@ -9294,6 +9396,7 @@ proc check_effective_target_vect_logical_reduc { } {
return [expr { [check_effective_target_aarch64_sve]
|| [istarget amdgcn-*-*]
|| [check_effective_target_riscv_v]
+ || [check_effective_target_loongarch_sx]
|| [istarget i?86-*-*] || [istarget x86_64-*-*]}]
}
@@ -9311,7 +9414,8 @@ proc check_effective_target_section_anchors { } {
return [check_cached_effective_target section_anchors {
expr { [istarget powerpc*-*-*]
|| [istarget arm*-*-*]
- || [istarget aarch64*-*-*] }}]
+ || [istarget aarch64*-*-*]
+ || [istarget loongarch*-*-*] }}]
}
# Return 1 if the target supports atomic operations on "int_128" values.
@@ -11623,8 +11727,10 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default compile
}
} elseif [istarget loongarch*-*-*] {
- lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx"
- if [check_effective_target_loongarch_asx_hw] {
+ # Set the default vectorization option to "-mlsx" due to the problem
+ # of non-aligned memory access when using 256-bit vectorization.
+ lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx"
+ if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
set dg-do-what-default compile
@@ -12190,7 +12296,8 @@ proc check_effective_target_builtin_eh_return { } {
proc check_effective_target_vect_max_reduc { } {
if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
- || [check_effective_target_riscv_v] } {
+ || [check_effective_target_riscv_v]
+ || [check_effective_target_loongarch_sx] } {
return 1
}
return 0
@@ -13205,7 +13312,7 @@ proc check_effective_target_loongarch_sx { } {
#if !defined(__loongarch_sx)
#error "LSX not defined"
#endif
- }]
+ } "-mlsx"]
}
proc check_effective_target_loongarch_sx_hw { } {
@@ -13225,7 +13332,7 @@ proc check_effective_target_loongarch_asx { } {
#if !defined(__loongarch_asx)
#error "LASX not defined"
#endif
- }]
+ } "-mlasx"]
}
proc check_effective_target_loongarch_asx_hw { } {
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 2/7] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12,23}.c file.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
2024-01-05 3:43 ` [PATCH v2 1/7] LoongArch: testsuite:Added support for vector object detection chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 3/7] LoongArch: testsuite:Added detection support for LoongArch architecture in vect-{82,83}.c chenxiaolong
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
Before modifying the test behavior of the program, dg-do is set to assemble in
vect-bic-bitmask-{12,23}.c. However, when the binutils library does not support
the vector instruction set, it will FAIL to recognize the vector instruction
and fail item will appear in the assembly stage. So set the program's dg-do to
compile.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-bic-bitmask-12.c: Change the default
setting of assembly to compile.
* gcc.dg/vect/vect-bic-bitmask-23.c: Dito.
---
gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c | 2 +-
gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c
index 36ec5a8b19b..213e4c2a418 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c
@@ -1,5 +1,5 @@
/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
-/* { dg-do assemble } */
+/* { dg-do compile } */
/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c
index 5b4c3b6e19b..5dceb4bbcb6 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c
@@ -1,5 +1,5 @@
/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
-/* { dg-do assemble } */
+/* { dg-do compile } */
/* { dg-additional-options "-O1 -fdump-tree-dce -w" } */
#include <stdint.h>
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 3/7] LoongArch: testsuite:Added detection support for LoongArch architecture in vect-{82,83}.c.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
2024-01-05 3:43 ` [PATCH v2 1/7] LoongArch: testsuite:Added support for vector object detection chenxiaolong
2024-01-05 3:43 ` [PATCH v2 2/7] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12,23}.c file chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 4/7] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90 chenxiaolong
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-82.c: Add the LoongArch architecture to the
object detection framework.
* gcc.dg/vect/vect-83.c: Dito.
---
gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +-
gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-82.c b/gcc/testsuite/gcc.dg/vect/vect-82.c
index 4b2d5a8a464..5c761e92a3a 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-82.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-82.c
@@ -1,4 +1,4 @@
-/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */
+/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */
/* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */
#include <stdarg.h>
diff --git a/gcc/testsuite/gcc.dg/vect/vect-83.c b/gcc/testsuite/gcc.dg/vect/vect-83.c
index 1a173daa140..7fe1b050cee 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-83.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-83.c
@@ -1,4 +1,4 @@
-/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */
+/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */
/* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */
#include <stdarg.h>
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 4/7] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
` (2 preceding siblings ...)
2024-01-05 3:43 ` [PATCH v2 3/7] LoongArch: testsuite:Added detection support for LoongArch architecture in vect-{82,83}.c chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 5/7] LoongArch: testsuite:Delete the default run behavior in pr60510.f chenxiaolong
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
On the LoongArch architecture, an error was found in the
bind_c_array_params_2.f90 file because there was no proper assembly code
for the regular expression detection function call, such as bl %plt(myBindC).
gcc/testsuite/ChangeLog:
* gfortran.dg/bind_c_array_params_2.f90: Add code test rules to
support testing of the loongArch architecture.
---
gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
index 0825efc7a2f..aa6a37b4850 100644
--- a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
+++ b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
@@ -2,6 +2,7 @@
! { dg-options "-std=f2008ts -fdump-tree-original" }
! { dg-additional-options "-mno-explicit-relocs" { target alpha*-*-* } }
! { dg-additional-options "-mno-relax-pic-calls" { target mips*-*-* } }
+! { dg-additional-options "-fplt -mcmodel=normal" { target loongarch*-*-* } }
!
! Check that assumed-shape variables are correctly passed to BIND(C)
! as defined in TS 29913
@@ -16,7 +17,8 @@ integer :: aa(4,4)
call test(aa)
end
-! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* } } } } }
+! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* loongarch*-*-* } } } } }
+! { dg-final { scan-assembler-times "bl\t%plt\\(myBindC\\)" 1 { target loongarch*-*-* } } }
! { dg-final { scan-assembler-times "myBindC,%r2" 1 { target { hppa*-*-* } } } }
! { dg-final { scan-assembler-times "call\tmyBindC" 1 { target { *-*-cygwin* *-*-ming* } } } }
! { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,myBindC" 1 { target { s390*-*-* } } } }
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 5/7] LoongArch: testsuite:Delete the default run behavior in pr60510.f.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
` (3 preceding siblings ...)
2024-01-05 3:43 ` [PATCH v2 4/7] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90 chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 6/7] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option chenxiaolong
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
When binutils does not support vector instruction sets, the test program fails
because it does not recognize vectorization at the assembly stage. Therefore,
the default run behavior of the program is deleted, so that the behavior of
the program depends on whether the software supports vectorization.
gcc/testsuite/ChangeLog:
* gfortran.dg/vect/pr60510.f: Delete the default behavior of the
program.
---
gcc/testsuite/gfortran.dg/vect/pr60510.f | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/testsuite/gfortran.dg/vect/pr60510.f b/gcc/testsuite/gfortran.dg/vect/pr60510.f
index 6cae82acece..d4fd42a664a 100644
--- a/gcc/testsuite/gfortran.dg/vect/pr60510.f
+++ b/gcc/testsuite/gfortran.dg/vect/pr60510.f
@@ -1,4 +1,3 @@
-! { dg-do run }
! { dg-require-effective-target vect_double }
! { dg-require-effective-target vect_intdouble_cvt }
! { dg-additional-options "-fno-inline -ffast-math" }
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 6/7] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
` (4 preceding siblings ...)
2024-01-05 3:43 ` [PATCH v2 5/7] LoongArch: testsuite:Delete the default run behavior in pr60510.f chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 3:43 ` [PATCH v2 7/7] LoongArch: testsuite:Give up the detection of the gcc.dg/fma-{3,4,6,7}.c file chenxiaolong
2024-01-05 12:29 ` [pushed][PATCH v2 0/7] LoongArch:Enable testing for common chenglulu
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
In the LoongArch architecture, the reason for not adding the 128-bit
vector-width-*hi* instruction template in the GCC back end is that it causes
program performance loss, so we can only add the "-mlasx" compilation option
to use 256-bit vectorization functions in test files.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pattern-1.c: If you are testing on the
LoongArch architecture, you need to add the "-mlasx" compilation
option to generate vectorized code.
* gcc.dg/vect/slp-widen-mult-half.c: Dito.
* gcc.dg/vect/vect-widen-mult-const-s16.c: Dito.
* gcc.dg/vect/vect-widen-mult-const-u16.c: Dito.
* gcc.dg/vect/vect-widen-mult-half-u8.c: Dito.
* gcc.dg/vect/vect-widen-mult-half.c: Dito.
* gcc.dg/vect/vect-widen-mult-u16.c: Dito.
* gcc.dg/vect/vect-widen-mult-u8-s16-s32.c: Dito.
* gcc.dg/vect/vect-widen-mult-u8-u32.c: Dito.
* gcc.dg/vect/vect-widen-mult-u8.c: Dito.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c | 1 +
gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c | 1 +
gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c | 1 +
10 files changed, 10 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c
index a3ff0f5b3da..5ae99225273 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */
#include <stdarg.h>
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
index 72811eb852e..b69ade33886 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
@@ -1,6 +1,7 @@
/* Disabling epilogues until we find a better way to deal with scans. */
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
index dfbb2171c00..53c9b84ca01 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c
@@ -2,6 +2,7 @@
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
/* { dg-additional-options "-fno-ipa-icf" } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
index c2ad58f69e7..e9db8285b66 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c
@@ -2,6 +2,7 @@
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
/* { dg-additional-options "-fno-ipa-icf" } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
index bfdcbaa09fb..607f3178f90 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
@@ -2,6 +2,7 @@
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
/* { dg-additional-options "-fno-ipa-icf" } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
index e46b0cc3135..cd13d826937 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
@@ -1,6 +1,7 @@
/* Disabling epilogues until we find a better way to deal with scans. */
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
index 14411ef43ed..258d253f401 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c
@@ -1,6 +1,7 @@
/* Disabling epilogues until we find a better way to deal with scans. */
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include <stdarg.h>
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
index f40def5dddf..3baafca7b54 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c
@@ -1,6 +1,7 @@
/* Disabling epilogues until we find a better way to deal with scans. */
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include <stdarg.h>
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
index 63866390835..bcfbe198a3f 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c
@@ -1,5 +1,6 @@
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */
#include <stdarg.h>
#include "tree-vect.h"
diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
index 78ad74b5d49..e3bf13b14fa 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c
@@ -1,5 +1,6 @@
/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */
#include <stdarg.h>
#include "tree-vect.h"
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 7/7] LoongArch: testsuite:Give up the detection of the gcc.dg/fma-{3,4,6,7}.c file.
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
` (5 preceding siblings ...)
2024-01-05 3:43 ` [PATCH v2 6/7] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option chenxiaolong
@ 2024-01-05 3:43 ` chenxiaolong
2024-01-05 12:29 ` [pushed][PATCH v2 0/7] LoongArch:Enable testing for common chenglulu
7 siblings, 0 replies; 9+ messages in thread
From: chenxiaolong @ 2024-01-05 3:43 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, chenxiaolong
On the LoongArch architecture, the above four test cases need to be waived
during testing. There are two situations:
1. The function of fma-{3,6}.c test is to find the value of c-a*b, but on
the LoongArch architecture, the function of the existing fnmsub instruction
is to find the value of -(a*b - c);
2. The function of fma-{4,7}.c test is to find the value of -(a*b)-c, but on
the LoongArch architecture, the function of the existing fnmadd instruction
is to find the value of -(a*b + c);
Through the analysis of the above two cases, there will be positive and
negative zero inequality.
gcc/testsuite/ChangeLog
* gcc.dg/fma-3.c: The intermediate file corresponding to the
function does not produce the corresponding FNMA symbol, so the test
rules should be skipped when testing.
* gcc.dg/fma-4.c: The intermediate file corresponding to the
function does not produce the corresponding FNMS symbol, so skip the
test rules when testing.
* gcc.dg/fma-6.c: The cause is the same as fma-3.c.
* gcc.dg/fma-7.c: The cause is the same as fma-4.c
---
gcc/testsuite/gcc.dg/fma-3.c | 2 +-
gcc/testsuite/gcc.dg/fma-4.c | 2 +-
gcc/testsuite/gcc.dg/fma-6.c | 2 +-
gcc/testsuite/gcc.dg/fma-7.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/fma-3.c b/gcc/testsuite/gcc.dg/fma-3.c
index 699aa2c9530..6649b54b6f9 100644
--- a/gcc/testsuite/gcc.dg/fma-3.c
+++ b/gcc/testsuite/gcc.dg/fma-3.c
@@ -12,4 +12,4 @@ f2 (double a, double b, double c)
return c - a * b;
}
-/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target scalar_all_fma } } } */
+/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/fma-4.c b/gcc/testsuite/gcc.dg/fma-4.c
index bff928f1fac..f1701c1961a 100644
--- a/gcc/testsuite/gcc.dg/fma-4.c
+++ b/gcc/testsuite/gcc.dg/fma-4.c
@@ -12,4 +12,4 @@ f2 (double a, double b, double c)
return -(a * b) - c;
}
-/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target scalar_all_fma } } } */
+/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/fma-6.c b/gcc/testsuite/gcc.dg/fma-6.c
index 87258cec4a2..9e49b62b6de 100644
--- a/gcc/testsuite/gcc.dg/fma-6.c
+++ b/gcc/testsuite/gcc.dg/fma-6.c
@@ -64,4 +64,4 @@ f10 (double a, double b, double c)
return -__builtin_fma (a, b, -c);
}
-/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target scalar_all_fma } } } */
+/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/fma-7.c b/gcc/testsuite/gcc.dg/fma-7.c
index f409cc8ee3c..86aacad7b90 100644
--- a/gcc/testsuite/gcc.dg/fma-7.c
+++ b/gcc/testsuite/gcc.dg/fma-7.c
@@ -64,4 +64,4 @@ f10 (double a, double b, double c)
return -__builtin_fma (a, b, c);
}
-/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target scalar_all_fma } } } */
+/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */
--
2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [pushed][PATCH v2 0/7] LoongArch:Enable testing for common
2024-01-05 3:43 [PATCH v2 0/7] LoongArch:Enable testing for common chenxiaolong
` (6 preceding siblings ...)
2024-01-05 3:43 ` [PATCH v2 7/7] LoongArch: testsuite:Give up the detection of the gcc.dg/fma-{3,4,6,7}.c file chenxiaolong
@ 2024-01-05 12:29 ` chenglulu
7 siblings, 0 replies; 9+ messages in thread
From: chenglulu @ 2024-01-05 12:29 UTC (permalink / raw)
To: chenxiaolong, gcc-patches; +Cc: xry111, i, xuchenghua
Pushed 2-7 to r14-6955...r14-6961.
在 2024/1/5 上午11:43, chenxiaolong 写道:
> v1->v2:
> On the basis of v1, the reason of the analysis problem is described in detail.
>
> When using binutils, which does not support vectorization, and the gcc compiler
> toolchain, which does support vectorization, the following two types of error
> problems occur in gcc regression testing.
>
> 1.Failure of common tests in the gcc.dg/vect directory．
>
> Regression testing of GCC has found that vect-bic-bitmask-{12/23}.c has errors
> at compile time, and similar problems exist on various architectures (e.g. x86,
> aarch64,riscv, etc.). The reason is that the behavior of the program is the
> assembly state, and the vector instruction cannot be recognized in the assembly
> stage and an error occurs.
>
> 2.FAIL items of common vectorization tests are supported.
>
> When LoongArch architecture supports common vector test cases, GCC regression
> testing has many failures. Reasons include a lack of detection of targets
> Rules, lack of vectorization options, lack of specific compilation options,
> check for instruction set differences and test behavior for program Settings,
> etc. For details, see the following patches:
>
> chenxiaolong (7):
> LoongArch: testsuite:Added support for vector object detection.
> LoongArch: testsuite:Modify the test behavior of the
> vect-bic-bitmask-{12,23}.c file.
> LoongArch: testsuite:Added detection support for LoongArch
> architecture in vect-{82,83}.c.
> LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90.
> LoongArch: testsuite:Delete the default run behavior in pr60510.f.
> LoongArch: testsuite:Added additional vectorization "-mlasx"
> compilation option.
> LoongArch: testsuite:Give up the detection of the
> gcc.dg/fma-{3,4,6,7}.c file.
>
> gcc/testsuite/gcc.dg/fma-3.c | 2 +-
> gcc/testsuite/gcc.dg/fma-4.c | 2 +-
> gcc/testsuite/gcc.dg/fma-6.c | 2 +-
> gcc/testsuite/gcc.dg/fma-7.c | 2 +-
> gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c | 1 +
> .../gcc.dg/vect/slp-widen-mult-half.c | 1 +
> gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +-
> gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +-
> .../gcc.dg/vect/vect-bic-bitmask-12.c | 2 +-
> .../gcc.dg/vect/vect-bic-bitmask-23.c | 2 +-
> .../gcc.dg/vect/vect-widen-mult-const-s16.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-const-u16.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-half-u8.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-half.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-u16.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-u8-s16-s32.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-u8-u32.c | 1 +
> .../gcc.dg/vect/vect-widen-mult-u8.c | 1 +
> .../gfortran.dg/bind_c_array_params_2.f90 | 4 +-
> gcc/testsuite/gfortran.dg/vect/pr60510.f | 1 -
> gcc/testsuite/lib/target-supports.exp | 217 +++++++++++++-----
> 21 files changed, 183 insertions(+), 65 deletions(-)
>
^ permalink raw reply [flat|nested] 9+ messages in thread