From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 4ED2C385840C for ; Fri, 5 Jan 2024 04:07:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4ED2C385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4ED2C385840C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704427642; cv=none; b=mOYahWWjx9nlc+VHBFR+2Z4uJKXUw2Y28662s2EfExSLvTOV4e2PWrmrjZw36kgLOCPY5HTJU9IUxtxcz5Ahu6LOXE/DhC1pEVtRINKuBRj7d4LS5VfGGF8xM/PfJxYDuRr8RjXErkkHveiWm2n3sWOiEbIlzCqKqGAvtZ2B2zU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704427642; c=relaxed/simple; bh=fRpVLPXEuQhv2yPhP6GrcgtmXsND85r/4ch5+O+M0jY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PNe7PK5oOSGdkJQ4GxplQf9Jd7z0Ua0rLZ0e/h+nbpYXQI75gl4AgUjdYYOIa5YNY9JBfCEdjE+axG11fUAanwFQvQKd/szFSXdtJiPoes/8JRevneZjB6LhXykoqPOYdMO2zI+CVM+w/J9s0stOUXExY6Qxfge5UowcAnpbM4M= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp73t1704427633t9xperkk Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 05 Jan 2024 12:07:12 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: k0mQ4ihyJQPSo88Bf3Ck0Y+eiV5vSHhKfW7/3uvVRFyyVGmNnVzOyQBHfqXS0 3jD64QbFK1nXf9AyjAcT+7P3vZk7UWCjG2GnwjZ8L8xTGKzKpkq8Mk+l4PTGYKA07hTFGak jJAp576veVMfTZzk6Pb1s+XhvG5DWONMoZ3dxzobAhiT1MW3AVkuKlUOljcMXiiAQVK/p3l 8s50KEiKvvXPVo7zkcSB2J51tA4WYnNIWOQ3wslNRpV7U/A7J2NaLf8JLGo9UpP+VrE+Pbh iDSSxs3uqTQ/PqjcH+dNQFKLpmkfDJqNV7wzZwfIuGFgzaLdS4GKYBcp7Gz1Z1S0NIJauKP ppfk0yBAN2euxyZNQ1d4tfeObNk5fz9DyWUTBSFEZDSMxOXwU7iBanBCez6xv9/16UuSZi4 sljpc1SnynkxjPWikLnQr+ZgDrc0k1IK X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5002076341158406898 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move Date: Fri, 5 Jan 2024 12:07:11 +0800 Message-Id: <20240105040711.2146204-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: While working on fixing a bug, I notice this following code has redundant move: #include "riscv_vector.h" void f (float x, float y, void *out) { float f[4] = { x, x, x, y }; vfloat32m1_t v = __riscv_vle32_v_f32m1 (f, 4); __riscv_vse32_v_f32m1 (out, v, 4); } Before this patch: f: vsetivli zero,4,e32,m1,ta,ma addi sp,sp,-16 vfmv.v.f v1,fa0 vfslide1down.vf v1,v1,fa1 vmv.v.v v1,v1 ----> redundant move. vse32.v v1,0(a0) addi sp,sp,16 jr ra The rootcause is that the complicate vmv.v.v pattern doesn't simplify it into simple (set (reg) (reg)) reg-to-reg move pattern. Currently, we support such simplification for VLMAX. However, the case I found is non-VLMAX but with LEN = NUNITS which should be considered as equivalent to VLMAX. Add a simple fix for such situation. Tested on both RV32/RV64 no regressions. Ok for trunk ? gcc/ChangeLog: * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function. * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto. * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-4.c: New test. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 21 +++++++++++++++++++ gcc/config/riscv/vector.md | 9 ++------ .../gcc.target/riscv/rvv/base/vf_avl-4.c | 13 ++++++++++++ 4 files changed, 37 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0f0337cfb38..064e8f443f3 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -687,6 +687,7 @@ bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); bool gather_scatter_valid_offset_p (machine_mode); HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); +bool whole_reg_to_reg_move_p (rtx *, machine_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index b7727b2b3e6..e5ba28d9078 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -5122,4 +5122,25 @@ estimated_poly_value (poly_int64 val, unsigned int kind) return val.coeffs[0] + val.coeffs[1] * over_min_vlen / TARGET_MIN_VLEN; } +/* Return true it is whole register-register move. */ +bool +whole_reg_to_reg_move_p (rtx *ops, machine_mode mode) +{ + if (register_operand (ops[0], mode) + && register_operand (ops[3], mode) + && satisfies_constraint_vu (ops[2]) + && satisfies_constraint_Wc1 (ops[1])) + { + int vlmax_index = GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL ? 5 : 7; + if (INTVAL (ops[vlmax_index]) == VLMAX) + return true; + /* AVL propagation PASS will transform FIXED-VLMAX with NUNITS < 32 + into NON-VLMAX with LEN = NUNITS. */ + else if (CONST_INT_P (ops[4]) + && known_eq (INTVAL (ops[4]), GET_MODE_NUNITS (mode))) + return true; + } + return false; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3d2c1c3ce8f..abd293f310c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1724,10 +1724,7 @@ vse.v\t%3,%0%p1 vmv.v.v\t%0,%3 vmv.v.v\t%0,%3" - "&& register_operand (operands[0], mode) - && register_operand (operands[3], mode) - && satisfies_constraint_vu (operands[2]) - && INTVAL (operands[7]) == riscv_vector::VLMAX" + "&& riscv_vector::whole_reg_to_reg_move_p (operands, mode)" [(set (match_dup 0) (match_dup 3))] "" [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov") @@ -1776,9 +1773,7 @@ vmmv.m\t%0,%3 vmclr.m\t%0 vmset.m\t%0" - "&& register_operand (operands[0], mode) - && register_operand (operands[3], mode) - && INTVAL (operands[5]) == riscv_vector::VLMAX" + "&& riscv_vector::whole_reg_to_reg_move_p (operands, mode)" [(set (match_dup 0) (match_dup 3))] "" [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c new file mode 100644 index 00000000000..1b4bfd96481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" +void +f (float x, float y, void *out) +{ + float f[4] = { x, x, x, y }; + vfloat32m1_t v = __riscv_vle32_v_f32m1 (f, 4); + __riscv_vse32_v_f32m1 (out, v, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */ -- 2.36.3