From: Daniel Cederman <cederman@gaisler.com>
To: gcc-patches@gcc.gnu.org
Cc: ebotcazou@libertysurf.fr, daniel@gaisler.com
Subject: [PATCH 2/2] sparc: Add errata workaround to membar patterns
Date: Fri, 5 Jan 2024 08:19:13 +0100 [thread overview]
Message-ID: <20240105071913.593978-4-cederman@gaisler.com> (raw)
In-Reply-To: <20240105071913.593978-1-cederman@gaisler.com>
LEON now uses the standard V8 membar patterns that contains an ldstub
instruction. This instruction needs to be aligned properly when the
GR712RC errata workaround is enabled.
gcc/ChangeLog:
* config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
* config/sparc/sync.md: Add GR712RC errata workaround
---
gcc/config/sparc/sparc.cc | 1 +
gcc/config/sparc/sync.md | 23 ++++++++++++++++++-----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index ebf1a557a49d..62c57cc53159 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -1052,6 +1052,7 @@ atomic_insn_for_leon3_p (rtx_insn *insn)
{
switch (INSN_CODE (insn))
{
+ case CODE_FOR_membar_storeload:
case CODE_FOR_swapsi:
case CODE_FOR_ldstub:
case CODE_FOR_atomic_compare_and_swap_leon3_1:
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index ac291420b8b9..fa249908a55f 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -65,12 +65,19 @@
[(set_attr "type" "multi")])
;; For V8, LDSTUB has the effect of membar #StoreLoad.
-(define_insn "*membar_storeload"
+(define_insn "membar_storeload"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
"TARGET_V8"
- "ldstub\t[%%sp-1], %%g0"
- [(set_attr "type" "multi")])
+{
+ if (sparc_fix_gr712rc)
+ return ".align\t16\n\tldstub\t[%%sp-1], %%g0";
+ else
+ return "ldstub\t[%%sp-1], %%g0";
+}
+ [(set_attr "type" "multi")
+ (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+ (const_int 4) (const_int 1)))])
;; Put the two together, in combination with the fact that V8 implements PSO
;; as its weakest memory model, means a full barrier. Match all remaining
@@ -80,9 +87,15 @@
(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
UNSPEC_MEMBAR))]
"TARGET_V8"
- "stbar\n\tldstub\t[%%sp-1], %%g0"
+{
+ if (sparc_fix_gr712rc)
+ return "stbar\n.align\t16\n\tldstub\t[%%sp-1], %%g0";
+ else
+ return "stbar\n\tldstub\t[%%sp-1], %%g0";
+}
[(set_attr "type" "multi")
- (set_attr "length" "2")])
+ (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+ (const_int 5) (const_int 2)))])
;; For V9, we have the full membar instruction.
(define_insn "*membar"
--
2.40.1
next prev parent reply other threads:[~2024-01-05 7:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-05 7:19 [PATCH] sparc: Char arrays are 64-bit aligned on SPARC Daniel Cederman
2024-01-05 7:19 ` [PATCH 1/2] sparc: Revert membar optimization that is not suitable for LEON5 Daniel Cederman
2024-01-08 9:22 ` Eric Botcazou
2024-01-05 7:19 ` [PATCH] sparc: Treat instructions with length 0 as empty Daniel Cederman
2024-01-08 9:26 ` Eric Botcazou
2024-01-05 7:19 ` Daniel Cederman [this message]
2024-01-08 9:32 ` [PATCH 2/2] sparc: Add errata workaround to membar patterns Eric Botcazou
2024-01-08 9:20 ` [PATCH] sparc: Char arrays are 64-bit aligned on SPARC Eric Botcazou
2024-01-08 11:42 ` Daniel Cederman
2024-01-09 8:45 ` Eric Botcazou
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