From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id ABCBC3857C4A for ; Thu, 11 Jan 2024 14:41:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ABCBC3857C4A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ABCBC3857C4A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::333 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704984103; cv=none; b=xi7SE5Qvjscj+yxgwzAFVb4Ngw6G9JA4E4RlJroaIu+U1ru+albEF5j8aKuBge4ZNT/fCwZFl9NW2J+RJn1Fd1RKjJeJO6xqk9Ab24WrVAWY6suexil7cUEWtJWYdchBSwgL7a5izxcmOHSUahlDpUobCN4+TxFWVMF4ztFUKRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704984103; c=relaxed/simple; bh=MJlYzhxluwovg0hc/HuOkNqX/BRDKAMu0PBerQ2tKpE=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=iLGxhzEwBzEm9ApzcHzWjKUPBk4mfyQL74ASG0LbjRWyjPJBLnw7ynkQulffwJCf8EC4461FeHw2C0IRImjU7kbMS1x9JAm5/GYOakO77KqpzfWSxH0scHWPhqjtzVGtD8f71cCJ4HxAFoPPebNspcgqM+QVIi5PzF5LYW6XJsY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40e5c317b34so10509035e9.2 for ; Thu, 11 Jan 2024 06:41:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1704984098; x=1705588898; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hGrY29t8qITR0TLFMNXfO2rtqR3KbkB8z5YcoYujwAk=; b=SUU+nKJGKeCSk8hRW/te95GbQw1+i3rRg1KKO7QjuxUBh8KJxkXMb8q8yfnshddg8M 8rV0BPcRaVg2lD2/2IegWMUciSS3gmjBo6z47Yz+0fTqmjcUcXCKE5FlhPmuGIFQYZal BhPgyJUKXmrvNejFBbNlw3CGKytx85oJS9yANr08x6Zu+9ImVSHQ3MtU1OzVx4Q3oIsz SQjwGhnaCXqhA0dtcBNRX8WMYvpT4Z76IdqMPQphWToEIJmwkYZgCB8uDRdB4nw95hig 1FlPhwM/mSkoUgsFW5Qjb7sDezC3xFsiWHHCZ/Z6Sm861zdOckgoZZ751glUHJrhQYW8 VKFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704984098; x=1705588898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hGrY29t8qITR0TLFMNXfO2rtqR3KbkB8z5YcoYujwAk=; b=sAtDC7DkxLRo45nMRSU+mO243qzGTiQx74EGI/5FhQMpQt9gSSNVinog006kDNcC6O lXxertQW2b5Oq92szi4Mi3v1JhySk/pMMyDpwszcl4pOpPKfFQ564bA4TxXv4LG39HIs 0Hst5A90ys21gyMLIanu4LWKbcVED+MsF9qBzecAmUp697C79+j0gyYigyWf1B/CcLeR zr8GyLlmuHWnUV/mLkEXPd4DEBZAUoBsgetbhkSrE14n6dL8iVo6iswvQFR2keMmVdLf 2rNX0DmFMbXrl1RWKwzhwJ7y4kuRxt6V+F5hA3rxDIH9kueLvpW+3mdXGeAHIo7tkVNu ZzlQ== X-Gm-Message-State: AOJu0YygQuTCbRbCEKCXM7HkdrCxOqpTqMQVTpfWgP8zOLO9uaJzM5uM g1YtxuBmlKiikmrytpehA/GyReXAyt+I197VYHoL/LooJGw8aw== X-Google-Smtp-Source: AGHT+IHZTI2vYJ6d3wv4wWMyX+e2btFMqohJIzTX0BPHNPL93k6XZXdNOI4+S6HZha0vB8MjHcA4oQ== X-Received: by 2002:a05:600c:538e:b0:40e:4b0d:286d with SMTP id hg14-20020a05600c538e00b0040e4b0d286dmr447751wmb.35.1704984097781; Thu, 11 Jan 2024 06:41:37 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id t6-20020a05600c198600b0040e48abec33sm6046161wmq.45.2024.01.11.06.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 06:41:37 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 0/1] RISC-V: Support CORE-V XCVMEM extension Date: Thu, 11 Jan 2024 14:41:17 +0000 Message-Id: <20240111144118.274895-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231109124219.966619-1-mary.bennett@embecosm.com> References: <20231109124219.966619-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MEM extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCVmem extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 29 ++ gcc/config/riscv/corev.md | 270 ++++++++++++++++++ gcc/config/riscv/predicates.md | 20 +- gcc/config/riscv/riscv-protos.h | 12 +- gcc/config/riscv/riscv.cc | 48 +++- gcc/config/riscv/riscv.h | 4 +- gcc/config/riscv/riscv.md | 26 +- gcc/config/riscv/riscv.opt | 2 + gcc/doc/sourcebuild.texi | 3 + .../gcc.target/riscv/cv-mem-lb-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lb-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lb-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lbu-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lbu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lbu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lh-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lh-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lh-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lhu-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lhu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lhu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lw-compile-1.c | 38 +++ .../gcc.target/riscv/cv-mem-lw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-lw-compile-3.c | 22 ++ .../riscv/cv-mem-operand-compile-1.c | 19 ++ .../riscv/cv-mem-operand-compile-2.c | 20 ++ .../riscv/cv-mem-operand-compile-3.c | 28 ++ .../riscv/cv-mem-operand-compile-4.c | 21 ++ .../riscv/cv-mem-operand-compile-5.c | 25 ++ .../riscv/cv-mem-operand-compile-6.c | 21 ++ .../riscv/cv-mem-operand-compile-7.c | 24 ++ .../riscv/cv-mem-operand-compile-8.c | 18 ++ .../gcc.target/riscv/cv-mem-sb-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sb-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sb-compile-3.c | 30 ++ .../gcc.target/riscv/cv-mem-sh-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sh-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sh-compile-3.c | 30 ++ .../gcc.target/riscv/cv-mem-sw-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sw-compile-3.c | 30 ++ gcc/testsuite/lib/target-supports.exp | 13 + 43 files changed, 1247 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c -- 2.34.1