[PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation

public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed

* [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation
@ 2024-01-12 18:08 Edwin Lu
  2024-01-12 18:08 ` [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
                   ` (3 more replies)
  0 siblings, 4 replies; 21+ messages in thread
From: Edwin Lu @ 2024-01-12 18:08 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu

Updates all tune insn reservation pipelines to cover all types defined by
define_attr "type" in riscv.md.

Creates new vector insn reservation pipelines in new file generic-vector-ooo.md
which has separate automaton vector_ooo where all reservations are mapped to.
This allows all tunes to share a common vector model for now as we make 
large changes to the vector cost model. 
(https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642511.html)

Disables pipeline scheduling for some tests with scan dump failures when using
-mtune=generic-ooo. 

Enables assert that all insn types must be associated with a dfa pipeline
reservation

Edwin Lu (4):
  RISC-V: Add non-vector types to dfa pipelines
  RISC-V: Add vector related pipelines
  RISC-V: Use default cost model for insn scheduling
  RISC-V: Enable assert for insn_has_dfa_reservation

---
V2:
- Update non-vector insn types and add new pipelines
- Add -fno-schedule-insn -fno-schedule-insn2 to some test cases

V3:
- Separate vector pipelines to separate file which all tunes have access to
---

 gcc/config/riscv/generic-ooo.md               | 138 ++-------------
 gcc/config/riscv/generic-vector-ooo.md        | 165 ++++++++++++++++++
 gcc/config/riscv/generic.md                   |  20 ++-
 gcc/config/riscv/riscv.cc                     |   6 +-
 gcc/config/riscv/riscv.md                     |  23 +--
 gcc/config/riscv/sifive-7.md                  |  17 +-
 gcc/config/riscv/vector.md                    |   2 +-
 gcc/config/riscv/zc.md                        |  96 +++++-----
 .../g++.target/riscv/rvv/base/bug-1.C         |   2 +
 .../riscv/rvv/autovec/reduc/reduc_call-2.c    |   2 +
 .../riscv/rvv/base/binop_vx_constraint-102.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-108.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-114.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-119.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-12.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-16.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-17.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-19.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-21.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-23.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-25.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-27.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-29.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-31.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-33.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-35.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-4.c    |   2 +
 .../riscv/rvv/base/binop_vx_constraint-40.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-44.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-50.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-56.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-62.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-68.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-74.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-79.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-8.c    |   2 +
 .../riscv/rvv/base/binop_vx_constraint-84.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-90.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-96.c   |   2 +
 .../rvv/base/float-point-dynamic-frm-30.c     |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-1.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-2.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-3.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-4.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-5.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-6.c    |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-7.c    |   2 +
 .../riscv/rvv/base/shift_vx_constraint-1.c    |   2 +
 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c     |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c     |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-32.c     |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-33.c     |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |   2 +
 gcc/testsuite/gfortran.dg/vect/vect-8.f90     |   2 +
 66 files changed, 391 insertions(+), 192 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines
  2024-01-12 18:08 [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation Edwin Lu
@ 2024-01-12 18:08 ` Edwin Lu
  2024-01-25 17:06   ` Robin Dapp
  2024-01-12 18:08 ` [PATCH V3 2/4] RISC-V: Add vector related pipelines Edwin Lu
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-12 18:08 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu

This patch adds non-vector related insn reservations and updates/creates
new insn reservations so all non-vector typed instructions have a reservation.

gcc/ChangeLog:

	* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
	(generic_ooo_branch): ditto
	* config/riscv/generic.md ( dittogeneric_sfb_alu):
	(generic_fmul_half): ditto
	* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
	* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
	(sifive_7_popcount): ditto
	* config/riscv/vector.md: change rdfrm to fmove
	* config/riscv/zc.md: change pushpop to load/store

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3:
- No changes
---
 gcc/config/riscv/generic-ooo.md | 15 +++++-
 gcc/config/riscv/generic.md     | 20 +++++--
 gcc/config/riscv/riscv.md       | 18 +++----
 gcc/config/riscv/sifive-7.md    | 17 +++++-
 gcc/config/riscv/vector.md      |  2 +-
 gcc/config/riscv/zc.md          | 96 ++++++++++++++++-----------------
 6 files changed, 102 insertions(+), 66 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..ef8cb96daf4 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
        (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-			move,bitmanip,min,max,minu,maxu,clz,ctz"))
+			move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
+			condmove,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+  (and (eq_attr "tune" "generic_ooo")
+       (eq_attr "type" "sfb_alu"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+  (and (eq_attr "tune" "generic_ooo")
+       (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
 
 ;; Float move, convert and compare.
 (define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
        (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-		        vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+		        vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..45986cfea89 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+			move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
+			condmove,crypto,mvpair,zicond"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
@@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3
 
 (define_insn_reservation "generic_branch" 1
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "branch,jump,call,jalr"))
+       (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+  (and (eq_attr "tune" "generic")
+       (eq_attr "type" "sfb_alu"))
   "alu")
 
 (define_insn_reservation "generic_imul" 10
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "imul,clmul"))
+       (eq_attr "type" "imul,clmul,cpop"))
   "imuldiv*10")
 
 (define_insn_reservation "generic_idivsi" 34
@@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66
 	    (eq_attr "mode" "DI")))
   "imuldiv*66")
 
+(define_insn_reservation "generic_fmul_half" 5
+  (and (eq_attr "tune" "generic")
+       (and (eq_attr "type" "fadd,fmul,fmadd")
+	    (eq_attr "mode" "HF")))
+  "alu")
+
 (define_insn_reservation "generic_fmul_single" 5
   (and (eq_attr "tune" "generic")
        (and (eq_attr "type" "fadd,fmul,fmadd")
@@ -88,3 +101,4 @@ (define_insn_reservation "generic_fsqrt" 25
   (and (eq_attr "tune" "generic")
        (eq_attr "type" "fsqrt"))
   "fdivsqrt*25")
+
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 95753c75cfc..1ec3e165791 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -326,9 +326,7 @@ (define_attr "ext_enabled" "no,yes"
 ;; rotate   rotation instructions
 ;; atomic   atomic instructions
 ;; condmove	conditional moves
-;; cbo    cache block instructions
 ;; crypto cryptography instructions
-;; pushpop    zc push and pop instructions
 ;; mvpair    zc move pair instructions
 ;; zicond    zicond instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
@@ -468,8 +466,8 @@ (define_attr "type"
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
    rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
-   rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
+   vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
@@ -3653,7 +3651,7 @@ (define_insn "riscv_clean_<mode>"
     UNSPECV_CLEAN)]
   "TARGET_ZICBOM"
   "cbo.clean\t%a0"
-  [(set_attr "type" "cbo")]
+  [(set_attr "type" "store")]
 )
 
 (define_insn "riscv_flush_<mode>"
@@ -3661,7 +3659,7 @@ (define_insn "riscv_flush_<mode>"
     UNSPECV_FLUSH)]
   "TARGET_ZICBOM"
   "cbo.flush\t%a0"
-  [(set_attr "type" "cbo")]
+  [(set_attr "type" "store")]
 )
 
 (define_insn "riscv_inval_<mode>"
@@ -3669,7 +3667,7 @@ (define_insn "riscv_inval_<mode>"
     UNSPECV_INVAL)]
   "TARGET_ZICBOM"
   "cbo.inval\t%a0"
-  [(set_attr "type" "cbo")]
+  [(set_attr "type" "store")]
 )
 
 (define_insn "riscv_zero_<mode>"
@@ -3677,7 +3675,7 @@ (define_insn "riscv_zero_<mode>"
     UNSPECV_ZERO)]
   "TARGET_ZICBOZ"
   "cbo.zero\t%a0"
-  [(set_attr "type" "cbo")]
+  [(set_attr "type" "store")]
 )
 
 (define_insn "prefetch"
@@ -3693,7 +3691,7 @@ (define_insn "prefetch"
     default: gcc_unreachable ();
   }
 }
-  [(set_attr "type" "cbo")])
+  [(set_attr "type" "store")])
 
 (define_insn "riscv_prefetchi_<mode>"
   [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
@@ -3701,7 +3699,7 @@ (define_insn "riscv_prefetchi_<mode>"
               UNSPECV_PREI)]
   "TARGET_ZICBOP"
   "prefetch.i\t%a0"
-  [(set_attr "type" "cbo")])
+  [(set_attr "type" "store")])
 
 (define_expand "extv<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=r")
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index a63394c8c58..52904f546ed 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -34,7 +34,7 @@ (define_insn_reservation "sifive_7_fpstore" 1
 
 (define_insn_reservation "sifive_7_branch" 1
   (and (eq_attr "tune" "sifive_7")
-       (eq_attr "type" "branch"))
+       (eq_attr "type" "branch,ret,trap"))
   "sifive_7_B")
 
 (define_insn_reservation "sifive_7_sfb_alu" 2
@@ -59,7 +59,8 @@ (define_insn_reservation "sifive_7_div" 16
 
 (define_insn_reservation "sifive_7_alu" 2
   (and (eq_attr "tune" "sifive_7")
-       (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move"))
+       (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\
+			rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,crypto,mvpair,zicond"))
   "sifive_7_A|sifive_7_B")
 
 (define_insn_reservation "sifive_7_load_immediate" 1
@@ -67,6 +68,12 @@ (define_insn_reservation "sifive_7_load_immediate" 1
        (eq_attr "type" "nop,const,auipc"))
   "sifive_7_A|sifive_7_B")
 
+(define_insn_reservation "sifive_7_hfma" 5
+  (and (eq_attr "tune" "sifive_7")
+       (and (eq_attr "type" "fadd,fmul,fmadd")
+	    (eq_attr "mode" "HF")))
+  "sifive_7_B")
+
 (define_insn_reservation "sifive_7_sfma" 5
   (and (eq_attr "tune" "sifive_7")
        (and (eq_attr "type" "fadd,fmul,fmadd")
@@ -106,6 +113,12 @@ (define_insn_reservation "sifive_7_f2i" 3
        (eq_attr "type" "mfc"))
   "sifive_7_A")
 
+;; Popcount and clmul.
+(define_insn_reservation "sifive_7_popcount" 2
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "cpop,clmul"))
+  "sifive_7_A")
+
 (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
   "sifive_7_alu,sifive_7_branch")
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index c1a282a27b3..4a7d84765c6 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1036,7 +1036,7 @@ (define_insn "frrmsi"
 	(reg:SI FRM_REGNUM))]
   "TARGET_VECTOR"
   "frrm\t%0"
-  [(set_attr "type" "rdfrm")
+  [(set_attr "type" "fmove")
    (set_attr "mode" "SI")]
 )
 
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 216232cb9f2..462ab37569e 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
                        (const_int <slot0_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
                        (const_int <slot1_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
                        (const_int <slot2_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
                        (const_int <slot3_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
                        (const_int <slot4_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
                        (const_int <slot5_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
                        (const_int <slot6_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
                        (const_int <slot7_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
                       (const_int <slot8_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
                        (const_int <slot9_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
                        (const_int <slot10_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
                        (const_int <slot12_offset>))))]
   "TARGET_ZCMP"
   "cm.pop	{ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret	{ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
   [(set (reg:X SP_REGNUM)
@@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
    (use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popretz	{ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
 
 (define_insn "@gpr_multi_push_up_to_ra_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_<mode>"
                  (match_operand 0 "stack_push_up_to_ra_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s0_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_<mode>"
                  (match_operand 0 "stack_push_up_to_s0_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s1_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_<mode>"
                  (match_operand 0 "stack_push_up_to_s1_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s2_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_<mode>"
                  (match_operand 0 "stack_push_up_to_s2_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s3_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_<mode>"
                  (match_operand 0 "stack_push_up_to_s3_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s4_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_<mode>"
                  (match_operand 0 "stack_push_up_to_s4_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s5_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_<mode>"
                  (match_operand 0 "stack_push_up_to_s5_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s6_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_<mode>"
                  (match_operand 0 "stack_push_up_to_s6_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s7_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_<mode>"
                  (match_operand 0 "stack_push_up_to_s7_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s8_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_<mode>"
                  (match_operand 0 "stack_push_up_to_s8_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s9_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_<mode>"
                  (match_operand 0 "stack_push_up_to_s9_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 (define_insn "@gpr_multi_push_up_to_s11_<mode>"
   [(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_<mode>"
                  (match_operand 0 "stack_push_up_to_s11_operand" "I")))]
   "TARGET_ZCMP"
   "cm.push	{ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
 
 ;; ZCMP mv
 (define_insn "*mva01s<X:mode>"
-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V3 2/4] RISC-V: Add vector related pipelines
  2024-01-12 18:08 [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation Edwin Lu
  2024-01-12 18:08 ` [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
@ 2024-01-12 18:08 ` Edwin Lu
  2024-01-25 17:06   ` Robin Dapp
  2024-01-12 18:08 ` [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling Edwin Lu
  2024-01-12 18:08 ` [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
  3 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-12 18:08 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu, Robin Dapp

Creates new generic vector pipeline file common to all cpu tunes.
Moves all vector related pipelines from generic-ooo to generic-vector-ooo.
Creates new vector crypto related insn reservations. Add temporary attribute
for making changes to the vector cost model

gcc/ChangeLog:

	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
	(generic_ooo_vec_load): ditto
	(generic_ooo_vec_store): ditto
	(generic_ooo_vec_loadstore_seg): ditto
	(generic_ooo_vec_alu): ditto
	(generic_ooo_vec_fcmp): ditto
	(generic_ooo_vec_imul): ditto
	(generic_ooo_vec_fadd): ditto
	(generic_ooo_vec_fmul): ditto
	(generic_ooo_crypto): ditto
	(generic_ooo_perm): ditto
	(generic_ooo_vec_reduction): ditto
	(generic_ooo_vec_ordered_reduction): ditto
	(generic_ooo_vec_idiv): ditto
	(generic_ooo_vec_float_divsqrt): ditto
	(generic_ooo_vec_mask): ditto
	(generic_ooo_vec_vesetvl): ditto
	(generic_ooo_vec_setrm): ditto
	(generic_ooo_vec_readlen): ditto
	* config/riscv/riscv.md (no): add temporary attribute
	* config/riscv/generic-vector-ooo.md: to here

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
  pipelines
V3:
- Move all vector pipelines into separate file which defines all ooo vector
  reservations.
- Add temporary attribute while cost model changes.
---
 gcc/config/riscv/generic-ooo.md        | 125 -------------------
 gcc/config/riscv/generic-vector-ooo.md | 165 +++++++++++++++++++++++++
 gcc/config/riscv/riscv.md              |   5 +
 3 files changed, 170 insertions(+), 125 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index ef8cb96daf4..40e5104cde1 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -48,9 +48,6 @@ (define_automaton "generic_ooo")
 ;; Integer/float issue queues.
 (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo")
 
-;; Separate issue queue for vector instructions.
-(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo")
-
 ;; Integer/float execution units.
 (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo")
 (define_cpu_unit "fxu0,fxu1" "generic_ooo")
@@ -58,12 +55,6 @@ (define_cpu_unit "fxu0,fxu1" "generic_ooo")
 ;; Integer subunit for division.
 (define_cpu_unit "generic_ooo_div" "generic_ooo")
 
-;; Vector execution unit.
-(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo")
-
-;; Vector subunit that does mult/div/sqrt.
-(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo")
-
 ;; Shortcuts
 (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4")
 (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3")
@@ -92,25 +83,6 @@ (define_insn_reservation "generic_ooo_float_store" 6
        (eq_attr "type" "fpstore"))
   "generic_ooo_issue,generic_ooo_fxu")
 
-;; Vector load/store
-(define_insn_reservation "generic_ooo_vec_load" 6
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-(define_insn_reservation "generic_ooo_vec_store" 6
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector segment loads/stores.
-(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
-			vssegte,vssegts,vssegtux,vssegtox"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-
 ;; Generic integer instructions.
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
@@ -191,103 +163,6 @@ (define_insn_reservation "generic_ooo_popcount" 2
        (eq_attr "type" "cpop,clmul"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
-;; Regular vector operations and integer comparisons.
-(define_insn_reservation "generic_ooo_vec_alu" 3
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-		        vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector float comparison, conversion etc.
-(define_insn_reservation "generic_ooo_vec_fcmp" 3
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
-			vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
-			vfncvtftoi,vfncvtftof"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector integer multiplication.
-(define_insn_reservation "generic_ooo_vec_imul" 4
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector float addition.
-(define_insn_reservation "generic_ooo_vec_fadd" 4
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vfalu,vfwalu"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector float multiplication and FMA.
-(define_insn_reservation "generic_ooo_vec_fmul" 6
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector crypto, assumed to be a generic operation for now.
-(define_insn_reservation "generic_ooo_crypto" 4
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "crypto"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector permute.
-(define_insn_reservation "generic_ooo_perm" 3
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
-			vislide1down,vfslide1up,vfslide1down,vgather,vcompress"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector reduction.
-(define_insn_reservation "generic_ooo_vec_reduction" 8
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle")
-
-;; Vector ordered reduction, assume the latency number is for
-;; a 128-bit vector.  It is scaled in riscv_sched_adjust_cost
-;; for larger vectors.
-(define_insn_reservation "generic_ooo_vec_ordered_reduction" 10
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vfredo,vfwredo"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
-
-;; Vector integer division, assume not pipelined.
-(define_insn_reservation "generic_ooo_vec_idiv" 16
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vidiv"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
-
-;; Vector float divisions and sqrt, assume not pipelined.
-(define_insn_reservation "generic_ooo_vec_float_divsqrt" 16
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vfdiv,vfsqrt"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3")
-
-;; Vector mask operations.
-(define_insn_reservation "generic_ooo_vec_mask" 2
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
-			vfmovvf,vfmovfv"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector vsetvl.
-(define_insn_reservation "generic_ooo_vec_vesetvl" 1
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "vsetvl,vsetvl_pre"))
-  "generic_ooo_vxu_issue")
-
-;; Vector rounding mode setters, assume pipeline barrier.
-(define_insn_reservation "generic_ooo_vec_setrm" 20
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "wrvxrm,wrfrm"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_issue*3")
-
-;; Vector read vlen/vlenb.
-(define_insn_reservation "generic_ooo_vec_readlen" 4
-  (and (eq_attr "tune" "generic_ooo")
-       (eq_attr "type" "rdvlenb,rdvl"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_issue")
-
 ;; Transfer from/to coprocessor.  Assume not pipelined.
 (define_insn_reservation "generic_ooo_xfer" 4
   (and (eq_attr "tune" "generic_ooo")
diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md
new file mode 100644
index 00000000000..474200ac26d
--- /dev/null
+++ b/gcc/config/riscv/generic-vector-ooo.md
@@ -0,0 +1,165 @@
+;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
+;; Contributed by Andrew Waterman (andrew@sifive.com).
+;; Based on MIPS target for GNU compiler.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+;; Vector load/store
+
+(define_automaton "vector_ooo")
+
+;; Separate issue queue for vector instructions.
+(define_cpu_unit "vxu_ooo_issue" "vector_ooo")
+
+;; Vector execution unit.
+(define_cpu_unit "vxu_ooo_alu" "vector_ooo")
+
+;; Vector subunit that does mult/div/sqrt.
+(define_cpu_unit "vxu_ooo_multicycle" "vector_ooo")
+
+(define_insn_reservation "vec_load" 6
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+(define_insn_reservation "vec_store" 6
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector segment loads/stores.
+(define_insn_reservation "vec_loadstore_seg" 10
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
+		        vssegte,vssegts,vssegtux,vssegtox"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Regular vector operations and integer comparisons.
+(define_insn_reservation "vec_alu" 3
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
+		        vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
+		        vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector float comparison, conversion etc.
+(define_insn_reservation "vec_fcmp" 3
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
+		        vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
+		        vfncvtftoi,vfncvtftof"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector integer multiplication.
+(define_insn_reservation "vec_imul" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
+		        vghsh,vgmul"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector float addition.
+(define_insn_reservation "vec_fadd" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vfalu,vfwalu"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector float multiplication and FMA.
+(define_insn_reservation "vec_fmul" 6
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector crypto, assumed to be a generic operation for now.
+(define_insn_reservation "vec_crypto" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "crypto"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector crypto, AES
+(define_insn_reservation "vec_crypto_aes" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector crypto, sha
+(define_insn_reservation "vec_crypto_sha" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector crypto, SM3/4
+(define_insn_reservation "vec_crypto_sm" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector permute.
+(define_insn_reservation "vec_perm" 3
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
+		        vislide1down,vfslide1up,vfslide1down,vgather,vcompress"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector reduction.
+(define_insn_reservation "vec_reduction" 8
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
+  "vxu_ooo_issue,vxu_ooo_multicycle")
+
+;; Vector ordered reduction, assume the latency number is for
+;; a 128-bit vector.  It is scaled in riscv_sched_adjust_cost
+;; for larger vectors.
+(define_insn_reservation "vec_ordered_reduction" 10
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vfredo,vfwredo"))
+  "vxu_ooo_issue,vxu_ooo_multicycle*3")
+
+;; Vector integer division, assume not pipelined.
+(define_insn_reservation "vec_idiv" 16
+  (eq_attr "type" "vidiv")
+  "vxu_ooo_issue,vxu_ooo_multicycle*3")
+
+;; Vector float divisions and sqrt, assume not pipelined.
+(define_insn_reservation "vec_float_divsqrt" 16
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vfdiv,vfsqrt"))
+  "vxu_ooo_issue,vxu_ooo_multicycle*3")
+
+;; Vector mask operations.
+(define_insn_reservation "vec_mask" 2
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
+		        vfmovvf,vfmovfv"))
+  "vxu_ooo_issue,vxu_ooo_alu")
+
+;; Vector vsetvl.
+(define_insn_reservation "vec_vesetvl" 1
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "vsetvl,vsetvl_pre"))
+  "vxu_ooo_issue")
+
+;; Vector rounding mode setters, assume pipeline barrier.
+(define_insn_reservation "vec_setrm" 20
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "wrvxrm,wrfrm"))
+  "vxu_ooo_issue,vxu_ooo_issue*3")
+
+;; Vector read vlen/vlenb.
+(define_insn_reservation "vec_readlen" 4
+  (and (eq_attr "is_inorder" "no")
+       (eq_attr "type" "rdvlenb,rdvl"))
+  "vxu_ooo_issue,vxu_ooo_issue")
+
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1ec3e165791..a386d1aa694 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -664,6 +664,10 @@ (define_attr "tune"
   "generic,sifive_7,generic_ooo"
   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
 
+;; In order/Out of order
+(define_attr "is_inorder" "no,yes" (const_string "no"))
+
+
 ;; Describe a user's asm statement.
 (define_asm_attributes
   [(set_attr "type" "multi")])
@@ -3827,6 +3831,7 @@ (define_insn "*large_load_address"
 (include "generic.md")
 (include "sifive-7.md")
 (include "thead.md")
+(include "generic-vector-ooo.md")
 (include "generic-ooo.md")
 (include "vector.md")
 (include "vector-crypto.md")
-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-01-12 18:08 [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation Edwin Lu
  2024-01-12 18:08 ` [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
  2024-01-12 18:08 ` [PATCH V3 2/4] RISC-V: Add vector related pipelines Edwin Lu
@ 2024-01-12 18:08 ` Edwin Lu
  2024-01-25 17:06   ` Robin Dapp
  2024-01-12 18:08 ` [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
  3 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-12 18:08 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.

39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?

	PR target/113249

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-1.C: use default scheduling
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-1.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-2.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-3.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-4.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-5.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-6.c: ditto
	* gcc.target/riscv/rvv/base/pr108185-7.c: ditto
	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
	* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
	* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C                 | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c         | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c         | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c         | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c         | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-17.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-19.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-21.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-23.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-25.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-27.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-29.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-31.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-33.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-35.c          | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-40.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-44.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-50.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-56.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-62.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-68.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-74.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-79.c          | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-84.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-90.c          | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-96.c          | 2 ++
 .../gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c      | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c            | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c          | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c  | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c         | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c          | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c          | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c          | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c          | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c          | 2 ++
 .../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c          | 2 ++
 gcc/testsuite/gfortran.dg/vect/vect-8.f90                       | 2 ++
 58 files changed, 116 insertions(+)

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
index c1070f9eb16..6f62a64224d 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 template < class T > 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 7be22d60bf2..17a6b6f27fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "reduc_call-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
index 4b24b971cba..8386b42e9b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
index 99acc51b4ff..e2ed4b76a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
index d595c446503..61340be8362 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
index 0b51175f66c..0f1485e3c0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 634c12a4c0e..173ac625ada 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 651d61001c1..1edba8980b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index d19a9fda235..75340c3da6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index 16f431542d8..7e4aedc1cdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index 347c846dcbb..755e92a9cd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index bc414440ba2..2c82dc0688a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index ce3f3af9c3d..e2ac6a3d9e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 4946f84b916..436a0e85f3d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 5f2eede0422..72b321607c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 5f2eede0422..72b321607c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 88fcba60345..6908c78e19b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 88fcba60345..6908c78e19b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index 87a16453fea..ee1db1c41ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index c0321cefb9a..fb969eb50a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index ab0f13ba255..542f43eca49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
index 3893e17511d..31109a81ec3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
index b0ea553bf89..924f4507ba3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
index 350697d764d..659d8d9e702 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
index 0f138c5d3c6..63874605759 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
index f4cbf095357..a214d70cb2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
index d606078e85f..efa659b2752 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 9bf9ff59de7..6a26248096d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
index bca55b239f9..429fe129003 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
index 586e26499db..0cd0af76186 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
index d1bbb78f5ed..bb1690e81e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
index bf5772073f7..5b666a920da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index c3d0b10271a..4c6e88e7eed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index bd13ba916da..0844e3e8713 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 99928f7b1cc..49a574485fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 321cd5c818e..cef0a11b2d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 575a7842cdf..3f0d67726bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 95a11d37016..4ed658899f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
index 8f6f0b11f09..95b7ff97666 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index 250e017cc86..9e0b41ccba7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 110e55b3cbe..5e1859cd13b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index 4583504bd5a..f4f0e52971a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index f16f4b9c37d..7e01b81682b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index 43b443be6cb..5615cb1f97f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index 67855581fb2..c906b153ab8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 960c9bff765..006df7edf8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index 5f22e8d0e8e..cc6d8221516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index e5f35c0f018..9704e444d54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 0532c7d4207..476735dcb2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index b664c4b67eb..c7b7db33849 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 04c4b886eec..80ff75f6d2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 1404c9dc0d5..127dc7ff06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 1404c9dc0d5..127dc7ff06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index 609c68dfcbe..e19e869e241 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 043f17737ae..90eca5b1ae6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 0bedde84005..17b217bc82c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 0bedde84005..17b217bc82c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
index 938dfc29754..f77ec9fb87a 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
@@ -1,6 +1,8 @@
 ! { dg-do compile }
 ! { dg-require-effective-target vect_double }
 ! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" }
+! PR113249
+! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } }
 
 module lfk_prec
  integer, parameter :: dp=kind(1.d0)
-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-01-12 18:08 [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation Edwin Lu
                   ` (2 preceding siblings ...)
  2024-01-12 18:08 ` [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling Edwin Lu
@ 2024-01-12 18:08 ` Edwin Lu
  2024-01-25 17:06   ` Robin Dapp
  3 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-12 18:08 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu

Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
V2:
- No changes
V3:
- No changes
---
 gcc/config/riscv/riscv.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee1a57b321d..c428d3e4e58 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8215,9 +8215,11 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
      an assert so we can find and fix this problem.  */
-#if 0
+  if (! insn_has_dfa_reservation_p (insn)) {
+    print_rtl(stderr, insn);
+    fprintf(stderr, "%d", get_attr_type (insn));
+  }
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }
-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines
  2024-01-12 18:08 ` [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
@ 2024-01-25 17:06   ` Robin Dapp
  2024-02-01  1:41     ` [COMMITTED " Edwin Lu
  0 siblings, 1 reply; 21+ messages in thread
From: Robin Dapp @ 2024-01-25 17:06 UTC (permalink / raw)
  To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain

LGTM, thanks.

Regards
 Robin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines
  2024-01-12 18:08 ` [PATCH V3 2/4] RISC-V: Add vector related pipelines Edwin Lu
@ 2024-01-25 17:06   ` Robin Dapp
  2024-01-26 18:25     ` Edwin Lu
  0 siblings, 1 reply; 21+ messages in thread
From: Robin Dapp @ 2024-01-25 17:06 UTC (permalink / raw)
  To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain

Thanks, that looks better IMHO.

> +;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
> +;; Contributed by Andrew Waterman (andrew@sifive.com).
> +;; Based on MIPS target for GNU compiler.

You might want to change that, as well as the date.  While at
it you can also fix the broken date in my original file ;)

> +(define_insn_reservation "vec_load" 6
> +  (and (eq_attr "is_inorder" "no")
> +       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
> +  "vxu_ooo_issue,vxu_ooo_alu")

I would rather ditch the is_inorder attribute for now and define
"low" latencies as well as reservations explicitly once we're
sure rather than falling back to scheduler defaults. 

OK with those changes.

Regards
 Robin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-01-12 18:08 ` [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling Edwin Lu
@ 2024-01-25 17:06   ` Robin Dapp
  2024-01-26 18:31     ` Edwin Lu
  2024-02-01  1:41     ` [COMMITTED " Edwin Lu
  0 siblings, 2 replies; 21+ messages in thread
From: Robin Dapp @ 2024-01-25 17:06 UTC (permalink / raw)
  To: gcc-patches; +Cc: rdapp.gcc

> Use default cost model scheduling on these test cases. All these tests
> introduce scan dump failures with -mtune generic-ooo. Since the vector
> cost models are the same across all three tunes, some of the tests
> in PR113249 will be fixed with this patch series.

This is OK, thanks.

> 39 additional unique testsuite failures (scan dumps) will still be present.
> I don't know how optimal the new output is compared to the old. Should I update
> the testcase expected output to match the new scan dumps?

Currently, without vector op latency, the output should come close
to what's normally considered "good" (i.e. minimal number of vsetvls
and so on).  Therefore I'd suggest not to change the scan dumps to
much except when there is a real problem.  If you have a specific
example that you're unsure about we can discuss this on or off list.

Regards
 Robin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-01-12 18:08 ` [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
@ 2024-01-25 17:06   ` Robin Dapp
  2024-01-26 18:37     ` Edwin Lu
  2024-02-01  1:42     ` [COMMITTED " Edwin Lu
  0 siblings, 2 replies; 21+ messages in thread
From: Robin Dapp @ 2024-01-25 17:06 UTC (permalink / raw)
  To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain

>    /* If we ever encounter an insn without an insn reservation, trip
>       an assert so we can find and fix this problem.  */
> -#if 0
> +  if (! insn_has_dfa_reservation_p (insn)) {
> +    print_rtl(stderr, insn);
> +    fprintf(stderr, "%d", get_attr_type (insn));
> +  }
>    gcc_assert (insn_has_dfa_reservation_p (insn));
> -#endif
>  
>    return more - 1;
>  }

I was thinking about make the gcc_assert a gcc_checking_assert so,
in case we accidentally forget something at any point, it would
only gracefully degrade in a release build.  As we already have
a hard assert for the type the patch (and not many test with
enable checking anyway) this is OK IMHO.

I suppose you tested with all available -mtune options?

Regards
 Robin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines
  2024-01-25 17:06   ` Robin Dapp
@ 2024-01-26 18:25     ` Edwin Lu
  2024-01-30 19:39       ` Robin Dapp
  0 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-26 18:25 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
> Thanks, that looks better IMHO.
>
>> +;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
>> +;; Contributed by Andrew Waterman (andrew@sifive.com).
>> +;; Based on MIPS target for GNU compiler.
> You might want to change that, as well as the date.  While at
> it you can also fix the broken date in my original file ;)

Completely forgot about this. I'll update it :)

>> +(define_insn_reservation "vec_load" 6
>> +  (and (eq_attr "is_inorder" "no")
>> +       (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
>> +  "vxu_ooo_issue,vxu_ooo_alu")
> I would rather ditch the is_inorder attribute for now and define
> "low" latencies as well as reservations explicitly once we're
> sure rather than falling back to scheduler defaults.

I think removing the is_inorder attribute should be ok. I added it 
because I wanted to avoid having two matching insn reservations defined 
since matching solely on the type attribute should also match on all 
subsets as well (i.e. if eventually we add an insn reservation checking 
for type "vlde" and tune "generic-ooo", any "vlde" insn would map to 
both reservations)

For now I should just remove the is_inorder attribute. We will update 
the latencies and add new reservations after we know what they should 
be. Is that correct?

> OK with those changes.
>
> Regards
>   Robin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-01-25 17:06   ` Robin Dapp
@ 2024-01-26 18:31     ` Edwin Lu
  2024-01-26 18:31       ` Edwin Lu
  2024-02-01  1:41     ` [COMMITTED " Edwin Lu
  1 sibling, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-26 18:31 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches

On 1/25/2024 9:06 AM, Robin Dapp wrote:

>> 39 additional unique testsuite failures (scan dumps) will still be present.
>> I don't know how optimal the new output is compared to the old. Should I update
>> the testcase expected output to match the new scan dumps?
> 
> Currently, without vector op latency, the output should come close
> to what's normally considered "good" (i.e. minimal number of vsetvls
> and so on).  Therefore I'd suggest not to change the scan dumps to
> much except when there is a real problem.  If you have a specific
> example that you're unsure about we can discuss this on or off list.
> 

That sounds good to me! I don't have a specific example that stands out. 
It's mostly just not finding the expected number of vsetvls or the 
vector insns have been moved earlier or something like that.

Edwin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-01-26 18:31     ` Edwin Lu
@ 2024-01-26 18:31       ` Edwin Lu
  0 siblings, 0 replies; 21+ messages in thread
From: Edwin Lu @ 2024-01-26 18:31 UTC (permalink / raw)
  To: gcc-patches

On 1/25/2024 9:06 AM, Robin Dapp wrote:

>> 39 additional unique testsuite failures (scan dumps) will still be present.
>> I don't know how optimal the new output is compared to the old. Should I update
>> the testcase expected output to match the new scan dumps?
> 
> Currently, without vector op latency, the output should come close
> to what's normally considered "good" (i.e. minimal number of vsetvls
> and so on).  Therefore I'd suggest not to change the scan dumps to
> much except when there is a real problem.  If you have a specific
> example that you're unsure about we can discuss this on or off list.
> 

That sounds good to me! I don't have a specific example that stands out. 
It's mostly just not finding the expected number of vsetvls or the 
vector insns have been moved earlier or something like that.

Edwin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-01-25 17:06   ` Robin Dapp
@ 2024-01-26 18:37     ` Edwin Lu
  2024-01-26 18:37       ` Edwin Lu
  2024-02-01  1:42     ` [COMMITTED " Edwin Lu
  1 sibling, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-01-26 18:37 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>>     /* If we ever encounter an insn without an insn reservation, trip
>>        an assert so we can find and fix this problem.  */
>> -#if 0
>> +  if (! insn_has_dfa_reservation_p (insn)) {
>> +    print_rtl(stderr, insn);
>> +    fprintf(stderr, "%d", get_attr_type (insn));
>> +  }
>>     gcc_assert (insn_has_dfa_reservation_p (insn));
>> -#endif
>>   
>>     return more - 1;
>>   }

Oops accidentally left my debugging statements in the patch.

> 
> I was thinking about make the gcc_assert a gcc_checking_assert so,
> in case we accidentally forget something at any point, it would
> only gracefully degrade in a release build.  As we already have
> a hard assert for the type the patch (and not many test with
> enable checking anyway) this is OK IMHO.
> 
> I suppose you tested with all available -mtune options?


I ran the testsuite on all three tunes using linux rv64gcv. generic-ooo 
had some bugs fixed while rocket and sifive-7-series had around 37 new 
scan dump failures which I think is to be expected. No ICE's from the 
hard gcc_assert on any of the tunes so I think it should be fine as is.

Edwin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-01-26 18:37     ` Edwin Lu
@ 2024-01-26 18:37       ` Edwin Lu
  0 siblings, 0 replies; 21+ messages in thread
From: Edwin Lu @ 2024-01-26 18:37 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>>     /* If we ever encounter an insn without an insn reservation, trip
>>        an assert so we can find and fix this problem.  */
>> -#if 0
>> +  if (! insn_has_dfa_reservation_p (insn)) {
>> +    print_rtl(stderr, insn);
>> +    fprintf(stderr, "%d", get_attr_type (insn));
>> +  }
>>     gcc_assert (insn_has_dfa_reservation_p (insn));
>> -#endif
>>   
>>     return more - 1;
>>   }

Oops accidentally left my debugging statements in the patch.

> 
> I was thinking about make the gcc_assert a gcc_checking_assert so,
> in case we accidentally forget something at any point, it would
> only gracefully degrade in a release build.  As we already have
> a hard assert for the type the patch (and not many test with
> enable checking anyway) this is OK IMHO.
> 
> I suppose you tested with all available -mtune options?


I ran the testsuite on all three tunes using linux rv64gcv. generic-ooo 
had some bugs fixed while rocket and sifive-7-series had around 37 new 
scan dump failures which I think is to be expected. No ICE's from the 
hard gcc_assert on any of the tunes so I think it should be fine as is.

Edwin



^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines
  2024-01-26 18:25     ` Edwin Lu
@ 2024-01-30 19:39       ` Robin Dapp
  0 siblings, 0 replies; 21+ messages in thread
From: Robin Dapp @ 2024-01-30 19:39 UTC (permalink / raw)
  To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain

> I think removing the is_inorder attribute should be ok. I added it
> because I wanted to avoid having two matching insn reservations
> defined since matching solely on the type attribute should also match
> on all subsets as well (i.e. if eventually we add an insn reservation
> checking for type "vlde" and tune "generic-ooo", any "vlde" insn
> would map to both reservations)
Ah, I see.  Yes we should prevent that from happening and in case we
have two (or more) similarly named reservations that would both match
such an attribute would make sense I guess.  My preference would just
be to not just add it yet before we know what else we'll be needing.
Chance is, not a whole lot will change until the release ;)

> For now I should just remove the is_inorder attribute. We will update
> the latencies and add new reservations after we know what they should
> be. Is that correct?

Yes, that should work.

Regards
 Robin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines
  2024-01-25 17:06   ` Robin Dapp
@ 2024-02-01  1:41     ` Edwin Lu
  2024-02-01  1:41       ` Edwin Lu
  0 siblings, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:41 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
> LGTM, thanks.
> 
> Regards
>   Robin
> 

Committed!

Edwin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines
  2024-02-01  1:41     ` [COMMITTED " Edwin Lu
@ 2024-02-01  1:41       ` Edwin Lu
  0 siblings, 0 replies; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:41 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
> LGTM, thanks.
> 
> Regards
>   Robin
> 

Committed!

Edwin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-01-25 17:06   ` Robin Dapp
  2024-01-26 18:31     ` Edwin Lu
@ 2024-02-01  1:41     ` Edwin Lu
  2024-02-01  1:41       ` Edwin Lu
  1 sibling, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:41 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>> Use default cost model scheduling on these test cases. All these tests
>> introduce scan dump failures with -mtune generic-ooo. Since the vector
>> cost models are the same across all three tunes, some of the tests
>> in PR113249 will be fixed with this patch series.
> 
> This is OK, thanks.
> 
>> 39 additional unique testsuite failures (scan dumps) will still be present.
>> I don't know how optimal the new output is compared to the old. Should I update
>> the testcase expected output to match the new scan dumps?
> 
> Currently, without vector op latency, the output should come close
> to what's normally considered "good" (i.e. minimal number of vsetvls
> and so on).  Therefore I'd suggest not to change the scan dumps to
> much except when there is a real problem.  If you have a specific
> example that you're unsure about we can discuss this on or off list.
> 
> Regards
>   Robin
> 
> 

Committed!

Edwin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 3/4] RISC-V: Use default cost model for insn scheduling
  2024-02-01  1:41     ` [COMMITTED " Edwin Lu
@ 2024-02-01  1:41       ` Edwin Lu
  0 siblings, 0 replies; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:41 UTC (permalink / raw)
  To: gcc-patches

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>> Use default cost model scheduling on these test cases. All these tests
>> introduce scan dump failures with -mtune generic-ooo. Since the vector
>> cost models are the same across all three tunes, some of the tests
>> in PR113249 will be fixed with this patch series.
> 
> This is OK, thanks.
> 
>> 39 additional unique testsuite failures (scan dumps) will still be present.
>> I don't know how optimal the new output is compared to the old. Should I update
>> the testcase expected output to match the new scan dumps?
> 
> Currently, without vector op latency, the output should come close
> to what's normally considered "good" (i.e. minimal number of vsetvls
> and so on).  Therefore I'd suggest not to change the scan dumps to
> much except when there is a real problem.  If you have a specific
> example that you're unsure about we can discuss this on or off list.
> 
> Regards
>   Robin
> 
> 

Committed!

Edwin


^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-01-25 17:06   ` Robin Dapp
  2024-01-26 18:37     ` Edwin Lu
@ 2024-02-01  1:42     ` Edwin Lu
  2024-02-01  1:42       ` Edwin Lu
  1 sibling, 1 reply; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:42 UTC (permalink / raw)
  To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>>     /* If we ever encounter an insn without an insn reservation, trip
>>        an assert so we can find and fix this problem.  */
>> -#if 0
>> +  if (! insn_has_dfa_reservation_p (insn)) {
>> +    print_rtl(stderr, insn);
>> +    fprintf(stderr, "%d", get_attr_type (insn));
>> +  }
>>     gcc_assert (insn_has_dfa_reservation_p (insn));
>> -#endif
>>   
>>     return more - 1;
>>   }
> 
> I was thinking about make the gcc_assert a gcc_checking_assert so,
> in case we accidentally forget something at any point, it would
> only gracefully degrade in a release build.  As we already have
> a hard assert for the type the patch (and not many test with
> enable checking anyway) this is OK IMHO.
> 
> I suppose you tested with all available -mtune options?
> 
> Regards
>   Robin
> 
> 

Committed without the debugging stuff!

Edwin

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [COMMITTED V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation
  2024-02-01  1:42     ` [COMMITTED " Edwin Lu
@ 2024-02-01  1:42       ` Edwin Lu
  0 siblings, 0 replies; 21+ messages in thread
From: Edwin Lu @ 2024-02-01  1:42 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain

On 1/25/2024 9:06 AM, Robin Dapp wrote:
>>     /* If we ever encounter an insn without an insn reservation, trip
>>        an assert so we can find and fix this problem.  */
>> -#if 0
>> +  if (! insn_has_dfa_reservation_p (insn)) {
>> +    print_rtl(stderr, insn);
>> +    fprintf(stderr, "%d", get_attr_type (insn));
>> +  }
>>     gcc_assert (insn_has_dfa_reservation_p (insn));
>> -#endif
>>   
>>     return more - 1;
>>   }
> 
> I was thinking about make the gcc_assert a gcc_checking_assert so,
> in case we accidentally forget something at any point, it would
> only gracefully degrade in a release build.  As we already have
> a hard assert for the type the patch (and not many test with
> enable checking anyway) this is OK IMHO.
> 
> I suppose you tested with all available -mtune options?
> 
> Regards
>   Robin
> 
> 

Committed without the debugging stuff!

Edwin


^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2024-02-01  1:50 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-12 18:08 [PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation Edwin Lu
2024-01-12 18:08 ` [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
2024-01-25 17:06   ` Robin Dapp
2024-02-01  1:41     ` [COMMITTED " Edwin Lu
2024-02-01  1:41       ` Edwin Lu
2024-01-12 18:08 ` [PATCH V3 2/4] RISC-V: Add vector related pipelines Edwin Lu
2024-01-25 17:06   ` Robin Dapp
2024-01-26 18:25     ` Edwin Lu
2024-01-30 19:39       ` Robin Dapp
2024-01-12 18:08 ` [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling Edwin Lu
2024-01-25 17:06   ` Robin Dapp
2024-01-26 18:31     ` Edwin Lu
2024-01-26 18:31       ` Edwin Lu
2024-02-01  1:41     ` [COMMITTED " Edwin Lu
2024-02-01  1:41       ` Edwin Lu
2024-01-12 18:08 ` [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
2024-01-25 17:06   ` Robin Dapp
2024-01-26 18:37     ` Edwin Lu
2024-01-26 18:37       ` Edwin Lu
2024-02-01  1:42     ` [COMMITTED " Edwin Lu
2024-02-01  1:42       ` Edwin Lu

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).