From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id 42BD73858C42 for ; Thu, 18 Jan 2024 09:59:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 42BD73858C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 42BD73858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=15.184.82.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705571955; cv=none; b=UY4wAEKr1gMGYR5LP+E8keJeZx+UKXvZ9OXRO14WxyYpn4IbXWCOARF2+nxy2lVQsVPYyxpEIHAmPlnAkGuht0IwQ01NUo+a1PWvy4IkGVnj+RObAQfTOeBDrxnrMZNo/RHPMFUuAZ4n8REDD/bnBHIDjjmFG5AItx/wC8JT58M= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705571955; c=relaxed/simple; bh=i4ITtXguiQnsBQ1aawy+3orz4XY42GboXR7jfOrBrTw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NuOkrJmdJyfrGNXJUFEsTIOuKI104uGr85rMQKifPeJCzy0tQ5+5O4fpnN4buiY9OjaSVMC9EPxMFCDkcJf4OoLdTSJ44y36ZxWZ+2Ji0FNMuVBfVJCddzaqjd/904CrOE3DHVVeeTLyxLzy1gFt+XHMBH/rdXavdl5eXqEXzPo= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp84t1705571939t76j175u X-QQ-Originating-IP: 8LA5Xx9nxJokncNtAgRQNJyHftTUnfk8x+vmGS5PhI4= Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 18 Jan 2024 17:58:58 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBflGvjwt7W3yS5DExwx1guAFkBfQoWvBCVsPUVXdf+/wEG6i9paOl w3K4Y4xyHWlrO8svdJyUo95jACwkbF99flLvFIaXcW+2u65nX30AAwZ185ASz3/PtSQVzKk MB6zga6KnSXNoVSafDj8DOqDwtZZ6DQVRRxP9GAXzZYTNtC5NkTbxmd2D8ky2QiS1d16T7O PQ8KvE302pDWV8GgjEnve5IuXm3xB+Q6rLdcbk4vhH84YzB3V9xLejinsckgzTVqeaHYR9j 3H3Z1xEyyLs1vxRUAVZZMIHFAZ2B0mr024sv2XoHokx7poqpsjKjXgJh0Avg9J8iv5b1jni DzzGf+YgvLH3iJgT1XjNC3xm4fcSjEcHTI8slj+koeIiZM7uQaxw5bfybypjqeecuSyV1Gw 4S2gw6GEp3SNtXOl83K80g== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5694694978311754616 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Support vi variant for vec_cmp Date: Thu, 18 Jan 2024 17:58:57 +0800 Message-Id: <20240118095857.272830-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: While running various benchmarks, I notice we miss vi variant support for integer comparison. That is, we can vectorize code into vadd.vi but we can't vectorize into vmseq.vi. Consider this following case: void foo (int n, int **__restrict a) { int b; int c; int d; for (b = 0; b < n; b++) for (long e = 8; e > 0; e--) a[b][e] = a[b][e] == 15; } Before this patch: vsetivli zero,4,e32,m1,ta,ma vmv.v.i v4,15 vmv.v.i v3,1 vmv.v.i v2,0 .L3: ld a5,0(a1) addi a4,a5,4 addi a5,a5,20 vle32.v v1,0(a5) vle32.v v0,0(a4) vmseq.vv v0,v0,v4 After this patch: ld a5,0(a1) addi a4,a5,4 addi a5,a5,20 vle32.v v1,0(a5) vle32.v v0,0(a4) vmseq.vi v0,v0,15 It's the missing feature caused by our some mistakes, support vi variant for vec_cmp like other patterns (add, sub, ..., etc). Tested with no regression, ok for trunk ? gcc/ChangeLog: * config/riscv/autovec.md: Support vi variant. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: New test. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: New test. * gcc.target/riscv/rvv/autovec/cmp/macro.h: New test. --- gcc/config/riscv/autovec.md | 4 +-- .../riscv/rvv/autovec/cmp/cmp_vi-1.c | 16 +++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-2.c | 16 +++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-3.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-4.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-5.c | 16 +++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-6.c | 16 +++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-7.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-8.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/cmp/cmp_vi-9.c | 18 ++++++++++++ .../gcc.target/riscv/rvv/autovec/cmp/macro.h | 11 ++++++++ 11 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 706cd9717cb..5ec1c59bdd4 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -664,7 +664,7 @@ [(set (match_operand: 0 "register_operand") (match_operator: 1 "comparison_operator" [(match_operand:V_VLSI 2 "register_operand") - (match_operand:V_VLSI 3 "register_operand")]))] + (match_operand:V_VLSI 3 "nonmemory_operand")]))] "TARGET_VECTOR" { riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]), @@ -677,7 +677,7 @@ [(set (match_operand: 0 "register_operand") (match_operator: 1 "comparison_operator" [(match_operand:V_VLSI 2 "register_operand") - (match_operand:V_VLSI 3 "register_operand")]))] + (match_operand:V_VLSI 3 "nonmemory_operand")]))] "TARGET_VECTOR" { riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]), diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c new file mode 100644 index 00000000000..10c232f77bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "macro.h" + +CMP_VI (ne_char, char, n, !=, 15) +CMP_VI (ne_short, short, n, !=, 15) +CMP_VI (ne_int, int, n, !=, 15) +CMP_VI (ne_long, long, n, !=, 15) +CMP_VI (ne_unsigned_char, unsigned char, n, !=, 15) +CMP_VI (ne_unsigned_short, unsigned short, n, !=, 15) +CMP_VI (ne_unsigned_int, unsigned int, n, !=, 15) +CMP_VI (ne_unsigned_long, unsigned long, n, !=, 15) + +/* { dg-final { scan-assembler-times {vmsne\.vi} 16 } } */ +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c new file mode 100644 index 00000000000..92bea596cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "macro.h" + +CMP_VI (ne_char, char, n, !=, -16) +CMP_VI (ne_short, short, n, !=, -16) +CMP_VI (ne_int, int, n, !=, -16) +CMP_VI (ne_long, long, n, !=, -16) +CMP_VI (ne_unsigned_char, unsigned char, n, !=, -16) +CMP_VI (ne_unsigned_short, unsigned short, n, !=, -16) +CMP_VI (ne_unsigned_int, unsigned int, n, !=, -16) +CMP_VI (ne_unsigned_long, unsigned long, n, !=, -16) + +/* { dg-final { scan-assembler-times {vmsne\.vi} 13 } } */ +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c new file mode 100644 index 00000000000..c9003279b0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */ + +#include "macro.h" + +CMP_VI (ne_char, char, 4, !=, 15) +CMP_VI (ne_short, short, 4, !=, 15) +CMP_VI (ne_int, int, 4, !=, 15) +CMP_VI (ne_long, long, 4, !=, 15) +CMP_VI (ne_unsigned_char, unsigned char, 4, !=, 15) +CMP_VI (ne_unsigned_short, unsigned short, 4, !=, 15) +CMP_VI (ne_unsigned_int, unsigned int, 4, !=, 15) +CMP_VI (ne_unsigned_long, unsigned long, 4, !=, 15) + +/* { dg-final { scan-assembler-times {vmsne\.vi} 32 } } */ +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c new file mode 100644 index 00000000000..544ff751522 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */ + +#include "macro.h" + +CMP_VI (ne_char, char, 4, !=, -16) +CMP_VI (ne_short, short, 4, !=, -16) +CMP_VI (ne_int, int, 4, !=, -16) +CMP_VI (ne_long, long, 4, !=, -16) +CMP_VI (ne_unsigned_char, unsigned char, 4, !=, -16) +CMP_VI (ne_unsigned_short, unsigned short, 4, !=, -16) +CMP_VI (ne_unsigned_int, unsigned int, 4, !=, -16) +CMP_VI (ne_unsigned_long, unsigned long, 4, !=, -16) + +/* { dg-final { scan-assembler-times {vmsne\.vi} 20 } } */ +/* { dg-final { scan-assembler-not {vmsne\.vv} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c new file mode 100644 index 00000000000..b7a5a4397c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "macro.h" + +CMP_VI (eq_char, char, n, ==, 15) +CMP_VI (eq_short, short, n, ==, 15) +CMP_VI (eq_int, int, n, ==, 15) +CMP_VI (eq_long, long, n, ==, 15) +CMP_VI (eq_unsigned_char, unsigned char, n, ==, 15) +CMP_VI (eq_unsigned_short, unsigned short, n, ==, 15) +CMP_VI (eq_unsigned_int, unsigned int, n, ==, 15) +CMP_VI (eq_unsigned_long, unsigned long, n, ==, 15) + +/* { dg-final { scan-assembler-times {vmseq\.vi} 16 } } */ +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c new file mode 100644 index 00000000000..f297ac80bbd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "macro.h" + +CMP_VI (eq_char, char, n, ==, -16) +CMP_VI (eq_short, short, n, ==, -16) +CMP_VI (eq_int, int, n, ==, -16) +CMP_VI (eq_long, long, n, ==, -16) +CMP_VI (eq_unsigned_char, unsigned char, n, ==, -16) +CMP_VI (eq_unsigned_short, unsigned short, n, ==, -16) +CMP_VI (eq_unsigned_int, unsigned int, n, ==, -16) +CMP_VI (eq_unsigned_long, unsigned long, n, ==, -16) + +/* { dg-final { scan-assembler-times {vmseq\.vi} 13 } } */ +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c new file mode 100644 index 00000000000..63ded00947d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */ + +#include "macro.h" + +CMP_VI (eq_char, char, 4, ==, 15) +CMP_VI (eq_short, short, 4, ==, 15) +CMP_VI (eq_int, int, 4, ==, 15) +CMP_VI (eq_long, long, 4, ==, 15) +CMP_VI (eq_unsigned_char, unsigned char, 4, ==, 15) +CMP_VI (eq_unsigned_short, unsigned short, 4, ==, 15) +CMP_VI (eq_unsigned_int, unsigned int, 4, ==, 15) +CMP_VI (eq_unsigned_long, unsigned long, 4, ==, 15) + +/* { dg-final { scan-assembler-times {vmseq\.vi} 32 } } */ +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c new file mode 100644 index 00000000000..f29b5f12c51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */ + +#include "macro.h" + +CMP_VI (eq_char, char, 4, ==, -16) +CMP_VI (eq_short, short, 4, ==, -16) +CMP_VI (eq_int, int, 4, ==, -16) +CMP_VI (eq_long, long, 4, ==, -16) +CMP_VI (eq_unsigned_char, unsigned char, 4, ==, -16) +CMP_VI (eq_unsigned_short, unsigned short, 4, ==, -16) +CMP_VI (eq_unsigned_int, unsigned int, 4, ==, -16) +CMP_VI (eq_unsigned_long, unsigned long, 4, ==, -16) + +/* { dg-final { scan-assembler-times {vmseq\.vi} 20 } } */ +/* { dg-final { scan-assembler-not {vmseq\.vv} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c new file mode 100644 index 00000000000..bfc1a68a1e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "macro.h" + +CMP_VI (le_char, char, n, <=, 15) +CMP_VI (le_short, short, n, <=, 15) +CMP_VI (le_int, int, n, <=, 15) +CMP_VI (le_long, long, n, <=, 15) +CMP_VI (le_unsigned_char, unsigned char, n, <=, 15) +CMP_VI (le_unsigned_short, unsigned short, n, <=, 15) +CMP_VI (le_unsigned_int, unsigned int, n, <=, 15) +CMP_VI (le_unsigned_long, unsigned long, n, <=, 15) + +/* { dg-final { scan-assembler-times {vmsle\.vi} 7 } } */ +/* { dg-final { scan-assembler-times {vmsleu\.vi} 9 } } */ +/* { dg-final { scan-assembler-not {vmsle\.vv} } } */ +/* { dg-final { scan-assembler-not {vmsleu\.vv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h new file mode 100644 index 00000000000..3fe6ee89a99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h @@ -0,0 +1,11 @@ +#define CMP_VI(NAME, TYPE, NITERS, OP, IMM) \ + void NAME (int n, TYPE **__restrict a) \ + { \ + int b; \ + int c; \ + int d; \ + for (b = 0; b < NITERS; b++) \ + for (int e = 8; e > 0; e--) \ + a[b][e] = a[b][e] OP IMM; \ + } + -- 2.36.3