From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 8DAF23858C42 for ; Thu, 25 Jan 2024 14:03:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8DAF23858C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8DAF23858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::42b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706191385; cv=none; b=R/WuT6DiDDFAync8V/sgFZL7CsfccamxufXROhepaU2VkqIDvVF65SN3R9qKuCDQ0WSPVE3Xr7sa+zHMdcMSaMiHTctP82WlHZc8wbSIKbPSCFoihWxLuNHRUcTXQfGlSWuhXn/Zxus0erAmHjg3Ir7rLxoU273M/T+OJsmsxKE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706191385; c=relaxed/simple; bh=5EqUZk4ElN52kRckOplll3kCbaP+qNpHFDT5drB9+Ac=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=oWuryXh33QDU5Dtkq7RHQIbZzPhwrAegI3XxSaKFSN3n3940/MfuCP0HWJSX74TnB6T3BM4j4Go3+B+L+OQGoinjJbpCKnx/NOapMrfvsFzaQheQHKWBEFGjYvreKGvqTr35+dYljCKfc66n90BSyer2dO8NjZdMz7/Do9k7k/U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3392b045e0aso4607001f8f.2 for ; Thu, 25 Jan 2024 06:03:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1706191381; x=1706796181; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ACCPwYi4vE+jC9d87SjLtMn1WaDhgSo+Tdp2oXRl/a8=; b=MTR+0Vsp9MEbr47lUEUw7VNtnHNogbDsIyD2NKfpsrEqcolKH+CVV2OUbQlwWbHs9I rHKY7h8OZGAAQUVw2ppaOD590n1lYMuYJzfbCIWPtqOr783ukBn+DVT3JodKJnAdJKFm e+k+5iUJXGhjfT4EvOKxCadOdB3LEaP5B3LJukj8qheliiJtELe5bFX8DV9P1vvc1wI8 DsDvA7M1p3xoEJ8TDFwlUuVB8/qs8dq3sfV1If1/QMM5WipwYhhX1nUrHccXyZAf3K8X D64MCPGrQeYmR8cFgXP+sMt1yPEBL3aF/A3KbRAha2hpGnFrBjaxyt3p55SHJcKyNERz vPVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706191381; x=1706796181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ACCPwYi4vE+jC9d87SjLtMn1WaDhgSo+Tdp2oXRl/a8=; b=gg3ZxsimRnc4NM4Ps+Q1ChbvR+PyGYjF+x6XxtJhX6dC7v33QXfzS5ehlw3Q3qvuxz er6gPMC8OVMygnPwUb0AoxnUNRIwqXYZMXKfSlIxoFR3M5V+si/dzZw2Uodd9mj2MTZ7 kAjiANXdFgMO2xyH5CZODufgmKeU4St3FfqGaFJZR45JDjQPQ8Bc2ptS1UTopdB849d1 PMcLkzNgczWOpHQ3Vm0X0pc4Mn8mvBzFeOg7coroAHX/GwcaFy3fuaVX7wusOI3gaeT0 yDUHHzGn7guC8HqlQnD4oqwSPzYwob+zGspOepcpfXXJvOdJ4QL6B3vAD27CkRahhKDE xlgQ== X-Gm-Message-State: AOJu0YzUQxr2rGfcEnC8P+0q2eJkDLhPIQDcbQP6RbRFw4nGNmhhh0BH CAypKJGZgfqPKneSP0nTdvul2RbbNq9QLE8MBQG9ZKlJIn/SEKGXHeuHnONp5e2jwFshG6Cdhha ohvI= X-Google-Smtp-Source: AGHT+IGyBf/WCUvUdHPaW7k0zkFiE5m0ZRt4vCsEU6xGBhn8Lh+n5v1RiEJjeaamSeZJwZjqm1Fk1w== X-Received: by 2002:a5d:4c49:0:b0:339:58b4:6013 with SMTP id n9-20020a5d4c49000000b0033958b46013mr527864wrt.132.1706191380732; Thu, 25 Jan 2024 06:03:00 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id z17-20020a5d4d11000000b003392af92996sm13013997wrt.101.2024.01.25.06.02.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:03:00 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v3 0/1] RISC-V: Support CORE-V XCVMEM extension Date: Thu, 25 Jan 2024 14:02:48 +0000 Message-Id: <20240125140249.1502930-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231109124219.966619-1-mary.bennett@embecosm.com> References: <20231109124219.966619-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MEM extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCVmem extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 29 ++ gcc/config/riscv/corev.md | 270 ++++++++++++++++++ gcc/config/riscv/predicates.md | 20 +- gcc/config/riscv/riscv-protos.h | 12 +- gcc/config/riscv/riscv.cc | 48 +++- gcc/config/riscv/riscv.h | 4 +- gcc/config/riscv/riscv.md | 26 +- gcc/config/riscv/riscv.opt | 2 + gcc/doc/sourcebuild.texi | 3 + .../gcc.target/riscv/cv-mem-lb-compile-1.c | 21 ++ .../gcc.target/riscv/cv-mem-lb-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lb-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lbu-compile-1.c | 21 ++ .../gcc.target/riscv/cv-mem-lbu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lbu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lh-compile-1.c | 21 ++ .../gcc.target/riscv/cv-mem-lh-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lh-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lhu-compile-1.c | 21 ++ .../gcc.target/riscv/cv-mem-lhu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lhu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lw-compile-1.c | 33 +++ .../gcc.target/riscv/cv-mem-lw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-lw-compile-3.c | 22 ++ .../riscv/cv-mem-operand-compile-1.c | 19 ++ .../riscv/cv-mem-operand-compile-2.c | 20 ++ .../riscv/cv-mem-operand-compile-3.c | 28 ++ .../riscv/cv-mem-operand-compile-4.c | 21 ++ .../riscv/cv-mem-operand-compile-5.c | 25 ++ .../riscv/cv-mem-operand-compile-6.c | 21 ++ .../riscv/cv-mem-operand-compile-7.c | 24 ++ .../riscv/cv-mem-operand-compile-8.c | 18 ++ .../gcc.target/riscv/cv-mem-sb-compile-1.c | 32 +++ .../gcc.target/riscv/cv-mem-sb-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sb-compile-3.c | 30 ++ .../gcc.target/riscv/cv-mem-sh-compile-1.c | 32 +++ .../gcc.target/riscv/cv-mem-sh-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sh-compile-3.c | 30 ++ .../gcc.target/riscv/cv-mem-sw-compile-1.c | 32 +++ .../gcc.target/riscv/cv-mem-sw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sw-compile-3.c | 30 ++ gcc/testsuite/lib/target-supports.exp | 13 + 43 files changed, 1222 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c -- 2.34.1