From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2a07:de40:b251:101:10:150:64:2]) by sourceware.org (Postfix) with ESMTPS id 800493858407 for ; Mon, 29 Jan 2024 12:11:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 800493858407 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 800493858407 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a07:de40:b251:101:10:150:64:2 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706530287; cv=none; b=kzq8McR4hmz6jCX9DlepGxsTVHXS8sSRCXp0uyAAtU+jerUvLUmzOSsIp/AWRdg42hyhRvw5VLQBE2Nf/sQq5IpR7Sn+bCDGl7Pzv/yHSfVSkW5ai/s3dpW5/MeioXGITsDDGqhlK2vgUwknd5ejJ8O2WBdXjVYXAqHU6dtQV3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706530287; c=relaxed/simple; bh=wvcGka7fbZZuqNZh3CRMiCppS05Vfn9b6QX4K/iFyQU=; h=DKIM-Signature:DKIM-Signature:DKIM-Signature:DKIM-Signature:Date: From:To:Subject:MIME-Version; b=cGejT8F+4qucp8fEAa5TBnN5kEUZIr7rdP4kg6vhFi2olVLmiG/iRwJaWeBYcMZkmRF/Kv+3I0GGE7FUuU0K2MEjQ4ApMlqA3sVE+d0Ly/qb7L504zMYWwU34LYSDdtWL+Y3UBV88w3aheO/0lz6Yxbn6XML+rQOpNEQ7yXmFA0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [10.168.4.150] (unknown [10.168.4.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 422C11F7EB; Mon, 29 Jan 2024 12:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1706530284; h=from:from:reply-to:date:date:to:to:cc:cc:mime-version:mime-version: content-type:content-type; bh=iKmnS2aAWCJFj7ShRDV+p7G79RCAndUaT/S0n+EWDAY=; b=LB07hJJUi+lNPoFXMZarnY2CC54FVV5BaFmjLfWnTPq/pTQKRKn31yn7Y6cEDAkV5tlGNH Prxz00ytVk0sEAv7mKv1oGZz6ebDVNAcm73IzmxKhHe2s5fCC62q/QkMAYujmDDAmzaUe5 80pd6G+1eLiwqYuJBiTi/aYJV1L52uo= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1706530284; h=from:from:reply-to:date:date:to:to:cc:cc:mime-version:mime-version: content-type:content-type; bh=iKmnS2aAWCJFj7ShRDV+p7G79RCAndUaT/S0n+EWDAY=; b=NwBMZGaacYpWZezzoGEM9U8Cmjgx4TOTclv1mTSMeXKBIk0bhN3rWtrTUF47XUbllJVrTf GKq64ggw9UiQFODQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1706530284; h=from:from:reply-to:date:date:to:to:cc:cc:mime-version:mime-version: content-type:content-type; bh=iKmnS2aAWCJFj7ShRDV+p7G79RCAndUaT/S0n+EWDAY=; b=LB07hJJUi+lNPoFXMZarnY2CC54FVV5BaFmjLfWnTPq/pTQKRKn31yn7Y6cEDAkV5tlGNH Prxz00ytVk0sEAv7mKv1oGZz6ebDVNAcm73IzmxKhHe2s5fCC62q/QkMAYujmDDAmzaUe5 80pd6G+1eLiwqYuJBiTi/aYJV1L52uo= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1706530284; h=from:from:reply-to:date:date:to:to:cc:cc:mime-version:mime-version: content-type:content-type; bh=iKmnS2aAWCJFj7ShRDV+p7G79RCAndUaT/S0n+EWDAY=; b=NwBMZGaacYpWZezzoGEM9U8Cmjgx4TOTclv1mTSMeXKBIk0bhN3rWtrTUF47XUbllJVrTf GKq64ggw9UiQFODQ== Date: Mon, 29 Jan 2024 13:05:51 +0100 (CET) From: Richard Biener To: gcc-patches@gcc.gnu.org cc: Jakub Jelinek Subject: [PATCH] middle-end/113622 - handle store with variable index to register MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Authentication-Results: smtp-out2.suse.de; none X-Spam-Score: 1.34 X-Spamd-Result: default: False [1.34 / 50.00]; ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; NEURAL_HAM_LONG(-1.00)[-0.999]; MIME_GOOD(-0.10)[text/plain]; NEURAL_SPAM_SHORT(2.94)[0.978]; MISSING_MID(2.50)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; RCPT_COUNT_TWO(0.00)[2]; DBL_BLOCKED_OPENRESOLVER(0.00)[gcc.target:url]; FUZZY_BLOCKED(0.00)[rspamd.com]; RCVD_COUNT_ZERO(0.00)[0]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; BAYES_HAM(-3.00)[100.00%] X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,MISSING_MID,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Message-ID: <20240129120551.fraL8xxTXQuUm_vR32zHL_J9f-34I4pzJMe9nvyrdP8@z> The following implements storing to a non-MEM_P with a variable offset. We usually avoid this by forcing expansion to memory but this doesn't work for hard register variables. The solution is to spill and operate on the stack. Bootstrapped and tested on x86_64-unknown-linux-gnu, OK? I realize the flow is a bit awkward, but short of duplicating a lot of code I can't see a better way. Forcing some lowering on GIMPLE (creating the copy there) might be another away. But then we could possibly lower the whole vector indexing in a different way in the first place ... Thanks, Richard. PR middle-end/113622 * expr.cc (expand_assignment): Spill hard registers if we index them with a variable offset. * gcc.target/i386/pr113622-2.c: New testcase. * gcc.target/i386/pr113622-3.c: Likewise. --- gcc/expr.cc | 23 +++++++++++++++++++--- gcc/testsuite/gcc.target/i386/pr113622-2.c | 12 +++++++++++ gcc/testsuite/gcc.target/i386/pr113622-3.c | 12 +++++++++++ 3 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr113622-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr113622-3.c diff --git a/gcc/expr.cc b/gcc/expr.cc index ee822c11dce..f13f07a2324 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -6061,6 +6061,7 @@ expand_assignment (tree to, tree from, bool nontemporal) to_rtx = adjust_address (to_rtx, BLKmode, 0); } + rtx stemp = NULL_RTX, old_to_rtx = NULL_RTX; if (offset != 0) { machine_mode address_mode; @@ -6070,9 +6071,22 @@ expand_assignment (tree to, tree from, bool nontemporal) { /* We can get constant negative offsets into arrays with broken user code. Translate this to a trap instead of ICEing. */ - gcc_assert (TREE_CODE (offset) == INTEGER_CST); - expand_builtin_trap (); - to_rtx = gen_rtx_MEM (BLKmode, const0_rtx); + if (TREE_CODE (offset) == INTEGER_CST) + { + expand_builtin_trap (); + to_rtx = gen_rtx_MEM (BLKmode, const0_rtx); + } + /* Else spill for variable offset to the destination. We expect + to run into this only for hard registers. */ + else + { + gcc_assert (DECL_HARD_REGISTER (tem)); + stemp = assign_stack_temp (GET_MODE (to_rtx), + GET_MODE_SIZE (GET_MODE (to_rtx))); + emit_move_insn (stemp, to_rtx); + old_to_rtx = to_rtx; + to_rtx = stemp; + } } offset_rtx = expand_expr (offset, NULL_RTX, VOIDmode, EXPAND_SUM); @@ -6305,6 +6319,9 @@ expand_assignment (tree to, tree from, bool nontemporal) bitregion_start, bitregion_end, mode1, from, get_alias_set (to), nontemporal, reversep); + /* Move the temporary storage back to the non-MEM_P. */ + if (stemp) + emit_move_insn (old_to_rtx, stemp); } if (result) diff --git a/gcc/testsuite/gcc.target/i386/pr113622-2.c b/gcc/testsuite/gcc.target/i386/pr113622-2.c new file mode 100644 index 00000000000..7bcc12af27e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113622-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msse -w" } */ + +typedef double __attribute__ ((vector_size (16))) vec; +register vec a asm("xmm5"), b asm("xmm6"), c asm("xmm7"); + +void +test (void) +{ + for (int i = 0; i < 2; i++) + c[i] = a[i] < b[i] ? 0.1 : 0.2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr113622-3.c b/gcc/testsuite/gcc.target/i386/pr113622-3.c new file mode 100644 index 00000000000..ca79d4ac901 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113622-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msse" } */ + +typedef double __attribute__ ((vector_size (16))) vec; + +void +test (void) +{ + register vec a asm("xmm5"), b asm("xmm6"), c asm("xmm7"); + for (int i = 0; i < 2; i++) + c[i] = a[i] < b[i] ? 0.1 : 0.2; +} -- 2.35.3