From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id D0C66386183E for ; Thu, 1 Feb 2024 15:46:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D0C66386183E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D0C66386183E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706802366; cv=none; b=epS6m3iUWBMfnsVBrzud/vE5IVbHolH+nOp1e3Cqu73lT0gM8nq5AVqDJNsu+iatK4tcyiJNsBc1GxH67+cUd04/D9HRd04LS6h+XntJCixbm9keyKSAIFQ4mq2/QPM3oJAPGlQVUjrDYUqlc+TnJ8TJKQy/Cn/kfdugFYSomXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706802366; c=relaxed/simple; bh=XtXxYPoURfAPbWdWD9NgnzJZnrIJgxFFBaMlhSxBuEg=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=SgdJnPdDe7XDU+HMr9kmJQegQCXX9olUYsVTBnkB+jG2UTSdYtP99UU2tnhuOzn+HEFbUbe029UhA6p5fU0mI6Ah0sa3T4ej6c6R6WsqH2WyrFFLobd+pknDO+BGRtqaWQeGhQT13BggY0SsBGPwIKOeM3iOVPBQsEN6m+IUc8c= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp76t1706802353tekqmbr7 X-QQ-Originating-IP: Veg9UOgtpoC1l7+6ryHtJR5mqXt6LeLfQvFlhSbQnqg= Received: from server1.localdomain ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 01 Feb 2024 23:45:52 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: l1AKOOPZQsd/6A1uIaKkgeczU7G2tVh6v8DS1acacAXRXVQNUEJ1xYeYlzaO/ rzxo5QpZKVnRQY8a0if07I4FyrZJxfDxSmHkFOH1Y0fpN5aNfuOW7KLU8F1DfOYg8JQTx8f +P0TjuAZchdSypFms/7mYfex37AaM/32QIcnxwJ7T+4LN7qzEcq7l9PJoujqDgN9PCYy6iU hRa2K7LlzlyNaQuexubB8JdXg08/iXghkMw6pyVU6eDNmtYwDW4JvJjzYDH321LZOUPvw9Y V3sUc6tCb5yrMC4oy3Jykh9cI04crhQb1e5qEkmjbcgZCgoY1KYPnVr58gpAmm7bIEGNVyl LHK2QhVLuHhytSJWgkpbnk9luJVveRhRbdnk/KUg1MQJNPUf9rJvpukYeG8IQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2660739584460002276 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Allow LICM hoist POLY_INT configuration code sequence Date: Thu, 1 Feb 2024 23:45:50 +0800 Message-Id: <20240201154550.316746-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Realize in recent benchmark evaluation (coremark-pro zip-test): vid.v v2 vmv.v.i v5,0 .L9: vle16.v v3,0(a4) vrsub.vx v4,v2,a6 ---> LICM failed to hoist it outside the loop. The root cause is: (insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0) (reg:DI 223)) "rvv.c":11:9 208 {*movdi_64bit} -> Its result used by the following vrsub.vx then supress the hoist of the vrsub.vx (nil)) (insn 57 56 59 4 (set (reg:RVVMF2HI 216) (if_then_else:RVVMF2HI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 350) (const_int 2 [0x2]) repeated x2 (const_int 1 [0x1]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (minus:RVVMF2HI (vec_duplicate:RVVMF2HI (reg:HI 220)) (reg:RVVMF2HI 217)) (unspec:RVVMF2HI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF))) "rvv.c":11:9 6938 {pred_subrvvmf2hi_reverse_scalar} (expr_list:REG_DEAD (reg:HI 220) (nil))) This patch fixes it generate (set (reg:HI) (subreg:HI (reg:DI))) instead of (set (subreg:DI (reg:DI)) (reg:DI)). After this patch: vid.v v2 vrsub.vx v2,v2,a7 vmv.v.i v4,0 .L3: vle16.v v3,0(a4) Tested on both RV32 and RV64 no regression. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/poly_licm-1.c: New test. * gcc.target/riscv/rvv/autovec/poly_licm-2.c: New test. --- gcc/config/riscv/riscv.cc | 9 ++++--- .../riscv/rvv/autovec/poly_licm-1.c | 18 +++++++++++++ .../riscv/rvv/autovec/poly_licm-2.c | 27 +++++++++++++++++++ 3 files changed, 50 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 529ef5e84b7..6e22b43e618 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2711,16 +2711,17 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) (const_poly_int:HI [m, n]) (const_poly_int:SI [m, n]). */ rtx tmp = gen_reg_rtx (Pmode); - riscv_legitimize_poly_move (Pmode, gen_lowpart (Pmode, dest), tmp, - src); + rtx tmp2 = gen_reg_rtx (Pmode); + riscv_legitimize_poly_move (Pmode, tmp2, tmp, src); + emit_move_insn (dest, gen_lowpart (mode, tmp2)); } else { /* In RV32 system, handle (const_poly_int:SI [m, n]) (const_poly_int:DI [m, n]). In RV64 system, handle (const_poly_int:DI [m, n]). - FIXME: Maybe we could gen SImode in RV32 and then sign-extend to DImode, - the offset should not exceed 4GiB in general. */ + FIXME: Maybe we could gen SImode in RV32 and then sign-extend to + DImode, the offset should not exceed 4GiB in general. */ rtx tmp = gen_reg_rtx (mode); riscv_legitimize_poly_move (mode, dest, tmp, src); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c new file mode 100644 index 00000000000..b7da65f0996 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +extern int wsize; + +typedef unsigned short Posf; +#define NIL 0 + +void foo (Posf *p) +{ + register unsigned n, m; + do { + m = *--p; + *p = (Posf)(m >= wsize ? m-wsize : NIL); + } while (--n); +} + +/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*-1\s+vrsub\.vx\s+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c new file mode 100644 index 00000000000..ffb3c63149f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +typedef unsigned short uint16_t; + +void AAA (uint16_t *x, uint16_t *y, unsigned wsize, unsigned count) +{ + unsigned m = 0, n = count; + register uint16_t *p; + + p = x; + + do { + m = *--p; + *p = (uint16_t)(m >= wsize ? m-wsize : 0); + } while (--n); + + n = wsize; + p = y; + + do { + m = *--p; + *p = (uint16_t)(m >= wsize ? m-wsize : 0); + } while (--n); +} + +/* { dg-final { scan-assembler-times {vid\.v\s+v[0-9]+\s+vrsub\.vx\s+} 2 } } */ -- 2.36.1