From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 30D653858C50 for ; Sat, 3 Feb 2024 08:59:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 30D653858C50 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 30D653858C50 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706950784; cv=none; b=kZZ5dtzFC3dPAxfGTX0jmj4pDZC5QFPrSa5OK8qGkRGPbBAJ4xcDgzWBf9LDONrH+Hn6fz4kkhtIVqLaQ3sYVNoDRPOtVT0uCMln7p1AQGlmeprjLWT2kYsAIX74oox7C/sA6ugvGPnYbfr3bx7OZVgHM1ghplDdnz3ukNu5hN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706950784; c=relaxed/simple; bh=AFWmmXSnRabt6I311Ry4xza9/pnoo54PGYrZQmLMCYs=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=mR3EvvaJNPIL7IymWOlnN4KBCxswTwWAp7YRNCR9xeUCeOn66EjTx4IVhHxL4A6X2ffhmHZ6pDK0eElLauNP8kRAqiQbYK6yAIvJLm8o00HYx4aQlGAbR63Wkzfi+NFHhEmMFmaud+9ihlqSYhYFim0O9BWhCDEIa0+b3ZPsKnE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1706950780; bh=AFWmmXSnRabt6I311Ry4xza9/pnoo54PGYrZQmLMCYs=; h=From:To:Cc:Subject:Date:From; b=A99I+7JKFwwni4arHXJq+eZunNbZPiRimeCZ01wOejR7eepX8ykssBA+nxecfxEw3 eR+4oCkZbPTvKtsDJlLYMPQK1boGgL2SXyoN6tiBkTqkj82akNMxHcizd3ttqnLngS BOolf72wDEB5EWCqwWMRR7NtLFA+vRl3MaOXXHW0= Received: from stargazer.. (unknown [IPv6:240e:358:114e:9800:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 6325D66AE3; Sat, 3 Feb 2024 03:59:36 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH] LoongArch: Fix wrong LSX FP vector negation Date: Sat, 3 Feb 2024 16:58:54 +0800 Message-ID: <20240203085921.88049-1-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with LSX enabled. Use the vbitrevi.{d/w} instructions to simply reverse the sign bit instead. We are already doing this for LASX and now we can unify them into simd.md. gcc/ChangeLog: * config/loongarch/lsx.md (neg2): Remove the incorrect expand. * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr. (elmsgnbit): Likewise. (neg2): New define_insn. * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they are now instantiated in simd.md. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/lasx.md | 16 ---------------- gcc/config/loongarch/lsx.md | 11 ----------- gcc/config/loongarch/simd.md | 18 ++++++++++++++++++ 3 files changed, 18 insertions(+), 27 deletions(-) diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index e2115ffb884..ac84db7f0ce 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -3028,22 +3028,6 @@ (define_insn "absv8sf2" [(set_attr "type" "simd_logic") (set_attr "mode" "V8SF")]) -(define_insn "negv4df2" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (neg:V4DF (match_operand:V4DF 1 "register_operand" "f")))] - "ISA_HAS_LASX" - "xvbitrevi.d\t%u0,%u1,63" - [(set_attr "type" "simd_logic") - (set_attr "mode" "V4DF")]) - -(define_insn "negv8sf2" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (neg:V8SF (match_operand:V8SF 1 "register_operand" "f")))] - "ISA_HAS_LASX" - "xvbitrevi.w\t%u0,%u1,31" - [(set_attr "type" "simd_logic") - (set_attr "mode" "V8SF")]) - (define_insn "xvfmadd4" [(set (match_operand:FLASX 0 "register_operand" "=f") (fma:FLASX (match_operand:FLASX 1 "register_operand" "f") diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 7002edae4d4..b9b94b9079c 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -728,17 +728,6 @@ (define_expand "neg2" DONE; }) -(define_expand "neg2" - [(set (match_operand:FLSX 0 "register_operand") - (neg:FLSX (match_operand:FLSX 1 "register_operand")))] - "ISA_HAS_LSX" -{ - rtx reg = gen_reg_rtx (mode); - emit_move_insn (reg, CONST0_RTX (mode)); - emit_insn (gen_sub3 (operands[0], reg, operands[1])); - DONE; -}) - (define_expand "lsx_vrepli" [(match_operand:ILSX 0 "register_operand") (match_operand 1 "const_imm10_operand")] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index cb0a19447a1..00ff2823a4e 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -85,12 +85,21 @@ (define_mode_attr simdfmt [(V2DF "d") (V4DF "d") (define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l") (V4SF "w") (V8SF "w")]) +;; Suffix for integer mode in LSX or LASX instructions to operating FP +;; vectors using integer vector operations. +(define_mode_attr simdfmt_as_i [(V2DF "d") (V4DF "d") + (V4SF "w") (V8SF "w")]) + ;; Size of vector elements in bits. (define_mode_attr elmbits [(V2DI "64") (V4DI "64") (V4SI "32") (V8SI "32") (V8HI "16") (V16HI "16") (V16QI "8") (V32QI "8")]) +;; The index of sign bit in FP vector elements. +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63") + (V4SF "31") (V8SF "31")]) + ;; This attribute is used to form an immediate operand constraint using ;; "const__operand". (define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") @@ -457,6 +466,15 @@ (define_expand "reduc__scal_" DONE; }) +;; FP negation. +(define_insn "neg2" + [(set (match_operand:FVEC 0 "register_operand" "=f") + (neg:FVEC (match_operand:FVEC 1 "register_operand" "f")))] + "" + "vbitrevi.\t%0,%1," + [(set_attr "type" "simd_logic") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") -- 2.43.0