[PATCH 0/2] Some minor internal optabs related fixes

[PATCH 0/2] Some minor internal optabs related fixes

[Andrew Pinski]

While working on adding some new vector code to the aarch64 backend,
I was confused on which mode was supposed to be used for widen_ssum pattern
so I decided to improve the documentation so the next person won't be confused.

Andrew Pinski (2):
  doc: Fix some standard named pattern documentation modes
  doc: Add documentation of which operand matches the mode of the
    standard pattern name [PR113508]

 gcc/doc/md.texi | 41 +++++++++++++++++++++++++----------------
 1 file changed, 25 insertions(+), 16 deletions(-)

-- 
2.43.0

[PATCH 1/2] doc: Fix some standard named pattern documentation modes

[Andrew Pinski]

Currently these use `@var{m3}` but the 3 here is a literal 3
and not part of the mode itself so it should not be inside
the var. Fixed as such.

Built the documentation to make sure it looks correct now.

gcc/ChangeLog:

	* doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
	smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
	var.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
 gcc/doc/md.texi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index b0c61925120..274dd03d419 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5798,19 +5798,19 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
 equal or wider than the mode of the absolute difference. The result is placed
 in operand 0, which is of the same mode as operand 3.
 
-@cindex @code{widen_ssum@var{m3}} instruction pattern
-@cindex @code{widen_usum@var{m3}} instruction pattern
-@item @samp{widen_ssum@var{m3}}
-@itemx @samp{widen_usum@var{m3}}
+@cindex @code{widen_ssum@var{m}3} instruction pattern
+@cindex @code{widen_usum@var{m}3} instruction pattern
+@item @samp{widen_ssum@var{m}3}
+@itemx @samp{widen_usum@var{m}3}
 Operands 0 and 2 are of the same mode, which is wider than the mode of
 operand 1. Add operand 1 to operand 2 and place the widened result in
 operand 0. (This is used express accumulation of elements into an accumulator
 of a wider mode.)
 
-@cindex @code{smulhs@var{m3}} instruction pattern
-@cindex @code{umulhs@var{m3}} instruction pattern
-@item @samp{smulhs@var{m3}}
-@itemx @samp{umulhs@var{m3}}
+@cindex @code{smulhs@var{m}3} instruction pattern
+@cindex @code{umulhs@var{m}3} instruction pattern
+@item @samp{smulhs@var{m}3}
+@itemx @samp{umulhs@var{m}3}
 Signed/unsigned multiply high with scale. This is equivalent to the C code:
 @smallexample
 narrow op0, op1, op2;
@@ -5820,10 +5820,10 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
 where the sign of @samp{narrow} determines whether this is a signed
 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
 
-@cindex @code{smulhrs@var{m3}} instruction pattern
-@cindex @code{umulhrs@var{m3}} instruction pattern
-@item @samp{smulhrs@var{m3}}
-@itemx @samp{umulhrs@var{m3}}
+@cindex @code{smulhrs@var{m}3} instruction pattern
+@cindex @code{umulhrs@var{m}3} instruction pattern
+@item @samp{smulhrs@var{m}3}
+@itemx @samp{umulhrs@var{m}3}
 Signed/unsigned multiply high with round and scale. This is
 equivalent to the C code:
 @smallexample
@@ -5834,10 +5834,10 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
 where the sign of @samp{narrow} determines whether this is a signed
 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
 
-@cindex @code{sdiv_pow2@var{m3}} instruction pattern
-@cindex @code{sdiv_pow2@var{m3}} instruction pattern
-@item @samp{sdiv_pow2@var{m3}}
-@itemx @samp{sdiv_pow2@var{m3}}
+@cindex @code{sdiv_pow2@var{m}3} instruction pattern
+@cindex @code{sdiv_pow2@var{m}3} instruction pattern
+@item @samp{sdiv_pow2@var{m}3}
+@itemx @samp{sdiv_pow2@var{m}3}
 Signed division by power-of-2 immediate. Equivalent to:
 @smallexample
 signed op0, op1;
-- 
2.43.0

Re: [PATCH 1/2] doc: Fix some standard named pattern documentation modes

[Richard Biener]

On Thu, Feb 15, 2024 at 12:16 AM Andrew Pinski <quic_apinski@quicinc.com> wrote:
>
> Currently these use `@var{m3}` but the 3 here is a literal 3
> and not part of the mode itself so it should not be inside
> the var. Fixed as such.
>
> Built the documentation to make sure it looks correct now.

OK

> gcc/ChangeLog:
>
>         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
>         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
>         var.
>
> Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
> ---
>  gcc/doc/md.texi | 32 ++++++++++++++++----------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index b0c61925120..274dd03d419 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -5798,19 +5798,19 @@ is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
>  equal or wider than the mode of the absolute difference. The result is placed
>  in operand 0, which is of the same mode as operand 3.
>
> -@cindex @code{widen_ssum@var{m3}} instruction pattern
> -@cindex @code{widen_usum@var{m3}} instruction pattern
> -@item @samp{widen_ssum@var{m3}}
> -@itemx @samp{widen_usum@var{m3}}
> +@cindex @code{widen_ssum@var{m}3} instruction pattern
> +@cindex @code{widen_usum@var{m}3} instruction pattern
> +@item @samp{widen_ssum@var{m}3}
> +@itemx @samp{widen_usum@var{m}3}
>  Operands 0 and 2 are of the same mode, which is wider than the mode of
>  operand 1. Add operand 1 to operand 2 and place the widened result in
>  operand 0. (This is used express accumulation of elements into an accumulator
>  of a wider mode.)
>
> -@cindex @code{smulhs@var{m3}} instruction pattern
> -@cindex @code{umulhs@var{m3}} instruction pattern
> -@item @samp{smulhs@var{m3}}
> -@itemx @samp{umulhs@var{m3}}
> +@cindex @code{smulhs@var{m}3} instruction pattern
> +@cindex @code{umulhs@var{m}3} instruction pattern
> +@item @samp{smulhs@var{m}3}
> +@itemx @samp{umulhs@var{m}3}
>  Signed/unsigned multiply high with scale. This is equivalent to the C code:
>  @smallexample
>  narrow op0, op1, op2;
> @@ -5820,10 +5820,10 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
>  where the sign of @samp{narrow} determines whether this is a signed
>  or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
>
> -@cindex @code{smulhrs@var{m3}} instruction pattern
> -@cindex @code{umulhrs@var{m3}} instruction pattern
> -@item @samp{smulhrs@var{m3}}
> -@itemx @samp{umulhrs@var{m3}}
> +@cindex @code{smulhrs@var{m}3} instruction pattern
> +@cindex @code{umulhrs@var{m}3} instruction pattern
> +@item @samp{smulhrs@var{m}3}
> +@itemx @samp{umulhrs@var{m}3}
>  Signed/unsigned multiply high with round and scale. This is
>  equivalent to the C code:
>  @smallexample
> @@ -5834,10 +5834,10 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
>  where the sign of @samp{narrow} determines whether this is a signed
>  or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
>
> -@cindex @code{sdiv_pow2@var{m3}} instruction pattern
> -@cindex @code{sdiv_pow2@var{m3}} instruction pattern
> -@item @samp{sdiv_pow2@var{m3}}
> -@itemx @samp{sdiv_pow2@var{m3}}
> +@cindex @code{sdiv_pow2@var{m}3} instruction pattern
> +@cindex @code{sdiv_pow2@var{m}3} instruction pattern
> +@item @samp{sdiv_pow2@var{m}3}
> +@itemx @samp{sdiv_pow2@var{m}3}
>  Signed division by power-of-2 immediate. Equivalent to:
>  @smallexample
>  signed op0, op1;
> --
> 2.43.0
>

[PATCH 2/2] doc: Add documentation of which operand matches the mode of the standard pattern name [PR113508]

[Andrew Pinski]

In some of the standard pattern names, it is not obvious which mode is being used in the pattern
name. Is it operand 0, 1, or 2? Is it the wider mode or the narrower mode?
This fixes that so there is no confusion by adding a sentence to some of them.

Built the documentation to make sure that it builds.

gcc/ChangeLog:

	* doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
	usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
	smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
	Add sentence about what the mode m is.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
 gcc/doc/md.texi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 274dd03d419..33b37e79cd4 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5746,6 +5746,7 @@ Operand 1 and operand 2 are of the same mode. Their
 product, which is of a wider mode, is computed and added to operand 3.
 Operand 3 is of a mode equal or wider than the mode of the product. The
 result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
 
 Semantically the expressions perform the multiplication in the following signs
 
@@ -5763,6 +5764,7 @@ Operand 1 and operand 2 are of the same mode. Their
 product, which is of a wider mode, is computed and added to operand 3.
 Operand 3 is of a mode equal or wider than the mode of the product. The
 result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
 
 Semantically the expressions perform the multiplication in the following signs
 
@@ -5779,6 +5781,7 @@ Operand 1 must be unsigned and operand 2 signed. Their
 product, which is of a wider mode, is computed and added to operand 3.
 Operand 3 is of a mode equal or wider than the mode of the product. The
 result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
 
 Semantically the expressions perform the multiplication in the following signs
 
@@ -5797,6 +5800,7 @@ Operand 1 and operand 2 are of the same mode. Their absolute difference, which
 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
 equal or wider than the mode of the absolute difference. The result is placed
 in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
 
 @cindex @code{widen_ssum@var{m}3} instruction pattern
 @cindex @code{widen_usum@var{m}3} instruction pattern
@@ -5806,6 +5810,7 @@ Operands 0 and 2 are of the same mode, which is wider than the mode of
 operand 1. Add operand 1 to operand 2 and place the widened result in
 operand 0. (This is used express accumulation of elements into an accumulator
 of a wider mode.)
+@var{m} is the mode of operand 1.
 
 @cindex @code{smulhs@var{m}3} instruction pattern
 @cindex @code{umulhs@var{m}3} instruction pattern
@@ -5819,6 +5824,8 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
 @end smallexample
 where the sign of @samp{narrow} determines whether this is a signed
 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
+@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
+and is defined to fit the whole multiply.
 
 @cindex @code{smulhrs@var{m}3} instruction pattern
 @cindex @code{umulhrs@var{m}3} instruction pattern
@@ -5833,6 +5840,8 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
 @end smallexample
 where the sign of @samp{narrow} determines whether this is a signed
 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
+@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
+and is defined to fit the whole multiply.
 
 @cindex @code{sdiv_pow2@var{m}3} instruction pattern
 @cindex @code{sdiv_pow2@var{m}3} instruction pattern
-- 
2.43.0

Re: [PATCH 2/2] doc: Add documentation of which operand matches the mode of the standard pattern name [PR113508]

[Richard Biener]

On Thu, Feb 15, 2024 at 12:16 AM Andrew Pinski <quic_apinski@quicinc.com> wrote:
>
> In some of the standard pattern names, it is not obvious which mode is being used in the pattern
> name. Is it operand 0, 1, or 2? Is it the wider mode or the narrower mode?
> This fixes that so there is no confusion by adding a sentence to some of them.
>
> Built the documentation to make sure that it builds.

OK.

> gcc/ChangeLog:
>
>         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
>         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
>         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
>         Add sentence about what the mode m is.
>
> Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
> ---
>  gcc/doc/md.texi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 274dd03d419..33b37e79cd4 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -5746,6 +5746,7 @@ Operand 1 and operand 2 are of the same mode. Their
>  product, which is of a wider mode, is computed and added to operand 3.
>  Operand 3 is of a mode equal or wider than the mode of the product. The
>  result is placed in operand 0, which is of the same mode as operand 3.
> +@var{m} is the mode of operand 1 and operand 2.
>
>  Semantically the expressions perform the multiplication in the following signs
>
> @@ -5763,6 +5764,7 @@ Operand 1 and operand 2 are of the same mode. Their
>  product, which is of a wider mode, is computed and added to operand 3.
>  Operand 3 is of a mode equal or wider than the mode of the product. The
>  result is placed in operand 0, which is of the same mode as operand 3.
> +@var{m} is the mode of operand 1 and operand 2.
>
>  Semantically the expressions perform the multiplication in the following signs
>
> @@ -5779,6 +5781,7 @@ Operand 1 must be unsigned and operand 2 signed. Their
>  product, which is of a wider mode, is computed and added to operand 3.
>  Operand 3 is of a mode equal or wider than the mode of the product. The
>  result is placed in operand 0, which is of the same mode as operand 3.
> +@var{m} is the mode of operand 1 and operand 2.
>
>  Semantically the expressions perform the multiplication in the following signs
>
> @@ -5797,6 +5800,7 @@ Operand 1 and operand 2 are of the same mode. Their absolute difference, which
>  is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
>  equal or wider than the mode of the absolute difference. The result is placed
>  in operand 0, which is of the same mode as operand 3.
> +@var{m} is the mode of operand 1 and operand 2.
>
>  @cindex @code{widen_ssum@var{m}3} instruction pattern
>  @cindex @code{widen_usum@var{m}3} instruction pattern
> @@ -5806,6 +5810,7 @@ Operands 0 and 2 are of the same mode, which is wider than the mode of
>  operand 1. Add operand 1 to operand 2 and place the widened result in
>  operand 0. (This is used express accumulation of elements into an accumulator
>  of a wider mode.)
> +@var{m} is the mode of operand 1.
>
>  @cindex @code{smulhs@var{m}3} instruction pattern
>  @cindex @code{umulhs@var{m}3} instruction pattern
> @@ -5819,6 +5824,8 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
>  @end smallexample
>  where the sign of @samp{narrow} determines whether this is a signed
>  or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
> +@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
> +and is defined to fit the whole multiply.
>
>  @cindex @code{smulhrs@var{m}3} instruction pattern
>  @cindex @code{umulhrs@var{m}3} instruction pattern
> @@ -5833,6 +5840,8 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
>  @end smallexample
>  where the sign of @samp{narrow} determines whether this is a signed
>  or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
> +@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
> +and is defined to fit the whole multiply.
>
>  @cindex @code{sdiv_pow2@var{m}3} instruction pattern
>  @cindex @code{sdiv_pow2@var{m}3} instruction pattern
> --
> 2.43.0
>