From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 2E14C3858432 for ; Mon, 26 Feb 2024 14:22:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E14C3858432 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2E14C3858432 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957363; cv=none; b=wIiM1U6XJm9q9RZTzU+y+AC47JHOQ9Wuw0AoAlJKZBxnVAN1/IiT1xwTkijvS4rDNPo+SUEoJjk1Vdn7aotbIZp7z8yT5soUlObfqzJyGTDp89w2jao96O2hVpsb9Vmc/lBFRehEj8PB4fYmMXt9ExilwQDkO3AuHJLFWFbVVHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957363; c=relaxed/simple; bh=FVI6UW8mYDed9Q/3Q3e89FVljzCPA7C+0D09+bbrd2Y=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Rtq0L0q5M9zkSgg3q9GpGOvWjuHk9JFHp1zZYGRWMoodK+MFYFI8AM+CKfMEbVmGilAWguvdCNplnfkMXYIPJgUu+IkNCzbq7HCtVo2NSe0qM2E8jRY2HRpRB03rD8M9IRm9goxHlTUbVBO/SAtipXWHVg3ZBWxFHQS3F8rSYpE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708957362; x=1740493362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FVI6UW8mYDed9Q/3Q3e89FVljzCPA7C+0D09+bbrd2Y=; b=mq+WNfcNbz+Bww77zY9Tq6pNA2Su1NQmzAeadboSRkSxCcuIa3S786/V ROkZRQAdjuG++PAezuepnKSWzKXe0gdP9qCcUmi9kHJ2S0yDedrsWxeBc i/ZaOcM6l74LqC1WYr4qgsz75Yp5j/1QCR8JFIfZ1yFcpUmWRv96BOoNU 1eFm2KafRXGBc6VSK4IUQyniZQ28PgTLq6EdcfZnMRpgez0z2aoy8etex y4M3nooS6WEVVWhZrl4NsvrhAucOBBmnQt8pU2x4xwi/eRXd5e6lRxoqk oDXcTYejyjTA1s8hhsbewpodRHirJ/VPjKBziKJhBh8xEoLHIjslKoM4V w==; X-IronPort-AV: E=McAfee;i="6600,9927,10995"; a="14678340" X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="14678340" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2024 06:22:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="7032021" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa007.jf.intel.com with ESMTP; 26 Feb 2024 06:22:37 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id AD9901005690; Mon, 26 Feb 2024 22:22:36 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, richard.guenther@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val Date: Mon, 26 Feb 2024 22:22:35 +0800 Message-Id: <20240226142235.3215553-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240226032558.587912-1-pan2.li@intel.com> References: <20240226032558.587912-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li We allowed vector type for get_stored_val when read is less than or equal to store in previous. Unfortunately, we missed to adjust the validate_subreg part accordingly. When the vector type's size is less than vector register, it will be considered as invalid in the validate_subreg. Consider the validate_subreg is kind of a can with worms and we are in stage 4. We will fix the issue from the DES side, and make sure the subreg is valid for both the read_mode and store_mode before perform the real gen_lowpart. The below test are passed for this patch: * The x86 bootstrap test. * The x86 regression test. * The riscv regression test. * The aarch64 regression test. gcc/ChangeLog: * dse.cc (get_stored_val): Add validate_subreg check before perform the gen_lowpart for rtl. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/ssa-fre-44.c: Add compile option to trigger the ICE. * gcc.target/riscv/rvv/base/bug-6.c: New test. Signed-off-by: Pan Li --- gcc/dse.cc | 4 +++- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c diff --git a/gcc/dse.cc b/gcc/dse.cc index edc7a1dfecf..1596da91da0 100644 --- a/gcc/dse.cc +++ b/gcc/dse.cc @@ -1946,7 +1946,9 @@ get_stored_val (store_info *store_info, machine_mode read_mode, copy_rtx (store_info->const_rhs)); else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) - && targetm.modes_tieable_p (read_mode, store_mode)) + && targetm.modes_tieable_p (read_mode, store_mode) + && validate_subreg (read_mode, store_mode, copy_rtx (store_info->rhs), + subreg_lowpart_offset (read_mode, store_mode))) read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); else read_reg = extract_low_bits (read_mode, store_mode, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c index f79b4c142ae..624a00a4f32 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -fdump-tree-fre1" } */ +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ struct A { float x, y; }; struct B { struct A u; }; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c new file mode 100644 index 00000000000..5bb00b8f587 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c @@ -0,0 +1,22 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize" } */ + +struct A { float x, y; }; +struct B { struct A u; }; + +extern void bar (struct A *); + +float +f3 (struct B *x, int y) +{ + struct A p = {1.0f, 2.0f}; + struct A *q = &x[y].u; + + __builtin_memcpy (&q->x, &p.x, sizeof (float)); + __builtin_memcpy (&q->y, &p.y, sizeof (float)); + + bar (&p); + + return x[y].u.x + x[y].u.y; +} -- 2.34.1