From: Tamar Christina <tamar.christina@arm.com>
To: gcc-patches@gcc.gnu.org
Cc: nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com,
Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com
Subject: [PATCH]AArch64: Do not allow SIMD clones with simdlen 1 [PR113552][GCC 13/12/11 backport]
Date: Tue, 9 Apr 2024 13:32:25 +0100 [thread overview]
Message-ID: <patch-18353-tamar@arm.com> (raw)
Message-ID: <20240409123225.FnnD0YaLd0e3JC9gvIYZ-iYusb0rHoHOPodbxmipiJE@z> (raw)
[-- Attachment #1: Type: text/plain, Size: 3604 bytes --]
Hi All,
This is a backport of g:306713c953d509720dc394c43c0890548bb0ae07.
The AArch64 vector PCS does not allow simd calls with simdlen 1,
however due to a bug we currently do allow it for num == 0.
This causes us to emit a symbol that doesn't exist and we fail to link.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
OK for GCC 13,12,11 branches?.
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/113552
* config/aarch64/aarch64.cc
(aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
gcc/testsuite/ChangeLog:
PR tree-optimization/113552
* gcc.target/aarch64/pr113552.c: New test.
* gcc.target/aarch64/simd_pcs_attribute-3.c: Remove bogus check.
---
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index f546c48ae2d2bad2e34c6b72e5e3e30aba3c3bd6..cec614596c5532b6341ab814f700c4ffc737340f 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -27027,7 +27027,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
bool explicit_p)
{
tree t, ret_type;
- unsigned int elt_bits, count;
+ unsigned int elt_bits, count = 0;
unsigned HOST_WIDE_INT const_simdlen;
poly_uint64 vec_bits;
@@ -27100,8 +27100,17 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
if (known_eq (clonei->simdlen, 0U))
{
- count = 2;
- vec_bits = (num == 0 ? 64 : 128);
+ /* We don't support simdlen == 1. */
+ if (known_eq (elt_bits, 64))
+ {
+ count = 1;
+ vec_bits = 128;
+ }
+ else
+ {
+ count = 2;
+ vec_bits = (num == 0 ? 64 : 128);
+ }
clonei->simdlen = exact_div (vec_bits, elt_bits);
}
else
@@ -27121,6 +27130,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
return 0;
}
}
+
clonei->vecsize_int = vec_bits;
clonei->vecsize_float = vec_bits;
return count;
diff --git a/gcc/testsuite/gcc.target/aarch64/pr113552.c b/gcc/testsuite/gcc.target/aarch64/pr113552.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c96b061ed2b4fcc57e58925277f74d14f79c51f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr113552.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -march=armv8-a" } */
+
+__attribute__ ((__simd__ ("notinbranch"), const))
+double cos (double);
+
+void foo (float *a, double *b)
+{
+ for (int i = 0; i < 12; i+=3)
+ {
+ b[i] = cos (5.0 * a[i]);
+ b[i+1] = cos (5.0 * a[i+1]);
+ b[i+2] = cos (5.0 * a[i+2]);
+ }
+}
+
+/* { dg-final { scan-assembler-times {bl\t_ZGVnN2v_cos} 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
index 95f6a6803e889c02177ef10972962ed62d2095eb..c6dac6b104c94c9de89ed88dc5a73e185d2be125 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
@@ -18,7 +18,7 @@ double foo(double x)
}
/* { dg-final { scan-assembler-not {\.variant_pcs\tfoo} } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnM1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM2v_foo} 1 } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnN1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN2v_foo} 1 } } */
--
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diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index f546c48ae2d2bad2e34c6b72e5e3e30aba3c3bd6..cec614596c5532b6341ab814f700c4ffc737340f 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -27027,7 +27027,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
bool explicit_p)
{
tree t, ret_type;
- unsigned int elt_bits, count;
+ unsigned int elt_bits, count = 0;
unsigned HOST_WIDE_INT const_simdlen;
poly_uint64 vec_bits;
@@ -27100,8 +27100,17 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
if (known_eq (clonei->simdlen, 0U))
{
- count = 2;
- vec_bits = (num == 0 ? 64 : 128);
+ /* We don't support simdlen == 1. */
+ if (known_eq (elt_bits, 64))
+ {
+ count = 1;
+ vec_bits = 128;
+ }
+ else
+ {
+ count = 2;
+ vec_bits = (num == 0 ? 64 : 128);
+ }
clonei->simdlen = exact_div (vec_bits, elt_bits);
}
else
@@ -27121,6 +27130,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
return 0;
}
}
+
clonei->vecsize_int = vec_bits;
clonei->vecsize_float = vec_bits;
return count;
diff --git a/gcc/testsuite/gcc.target/aarch64/pr113552.c b/gcc/testsuite/gcc.target/aarch64/pr113552.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c96b061ed2b4fcc57e58925277f74d14f79c51f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr113552.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -march=armv8-a" } */
+
+__attribute__ ((__simd__ ("notinbranch"), const))
+double cos (double);
+
+void foo (float *a, double *b)
+{
+ for (int i = 0; i < 12; i+=3)
+ {
+ b[i] = cos (5.0 * a[i]);
+ b[i+1] = cos (5.0 * a[i+1]);
+ b[i+2] = cos (5.0 * a[i+2]);
+ }
+}
+
+/* { dg-final { scan-assembler-times {bl\t_ZGVnN2v_cos} 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
index 95f6a6803e889c02177ef10972962ed62d2095eb..c6dac6b104c94c9de89ed88dc5a73e185d2be125 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
@@ -18,7 +18,7 @@ double foo(double x)
}
/* { dg-final { scan-assembler-not {\.variant_pcs\tfoo} } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnM1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM2v_foo} 1 } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnN1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN2v_foo} 1 } } */
next reply other threads:[~2024-04-09 12:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-12 16:08 Tamar Christina [this message]
2024-04-09 12:32 ` Tamar Christina
2024-04-09 15:48 ` Richard Sandiford
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