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RISC-V

+
    +
  • The SLP and loop vectorizer is now enabled for RISC-V when the vector + extension is enabled, thanks to Ju-Zhe Zhong from + RiVAI, + Pan Li from Intel, and Robin Dapp + from Ventana Micro for + contributing most of the implementation!
  • +
  • The -mrvv-max-lmul= option has been introduced for + performance tuning of the loop vectorizer. The default value is + -mrvv-max-lmul=m1, which limits the maximum LMUL to 1. + The -mrvv-max-lmul=dynamic setting can dynamically select + the maximum LMUL value based on register pressure.
  • +
  • Atomic code generation has been improved and is now in conformance with + the latest psABI specification, thanks to Patrick O'Neill from + Rivos.
  • +
  • Support for the vector intrinsics as specified in + + version 1.0 of the RISC-V vector intrinsic specification.
  • +
  • Support for the experimental vector crypto intrinsics as specified in + + RISC-V vector intrinsic specification, thanks to Feng Wang et al. + from ESWIN Computing
  • +
  • Support for the T-head vector intrinsics.
  • +
  • Support for the scalar bitmanip and scalar crypto intrinsics, thanks to + Liao Shihua from PLCT.
  • +
  • Support for the large code model via option -mcmodel=large, + thanks to Kuan-Lin Chen from + Andes Technology.
  • +
  • Support for the standard vector calling convention variant, thanks to + Lehua Ding from RiVAI.
  • +
  • Supports the target attribute, which allows users to compile + a function with specific extensions.
  • +
  • -march= option no longer requires the architecture string + to be in canonical order, with only a few constraints remaining: the + architecture string must start with rv[32|64][i|g|e], and + must use an underscore as the separator after a multi-letter extension. +
  • +
  • -march=help option has been introduced to dump all + supported extensions.
  • +
  • Added experimental support for the -mrvv-vector-bits=zvl + option and the riscv_rvv_vector_bits attribute, which + specify a fixed length for scalable vector types. This option is + optimized for specific vector core implementations; however, the code + generated with this option is NOT portable, + thanks to Pan Li from Intel. +
  • +
  • Support for TLS descriptors has been introduced, which can be enabled by + the -mtls-dialect=desc option. The default behavior can be + configured with --with-tls=[trad|desc].
  • +
  • Support for the TLS descriptors, this can be enabled by + -mtls-dialect=desc and the default behavior can be configure + by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from + Blue Whale Systems +
  • +
  • Support for the following standard extensions has been added: +
      +
    • Vector crypto extensions: +
        +
      • Zvbb
      • +
      • Zvkb
      • +
      • Zvbc
      • +
      • Zvkg
      • +
      • Zvkned
      • +
      • Zvkhna
      • +
      • Zvkhnb
      • +
      • Zvksed
      • +
      • Zvksh
      • +
      • Zvkn
      • +
      • Zvknc
      • +
      • Zvkng
      • +
      • Zvks
      • +
      • Zvksc
      • +
      • Zvksg
      • +
      • Zvkt
      • +
      +
    • +
    • Code size reduction extensions: +
        +
      • Zca
      • +
      • Zcb
      • +
      • Zce
      • +
      • Zcf
      • +
      • Zcd
      • +
      • Zcmp
      • +
      • Zcmt
      • +
      +
    • +
    • Zicond
    • +
    • Zfa
    • +
    • Ztso
    • +
    • Zvfbfmin
    • +
    • Zvfhmin
    • +
    • Zvfh
    • +
    • Za64rs
    • +
    • Za128rs
    • +
    • Ziccif
    • +
    • Ziccrse
    • +
    • Ziccamoa
    • +
    • Zicclsm
    • +
    • Zic64b
    • +
    • Smaia
    • +
    • Smepmp
    • +
    • Smstateen
    • +
    • Ssaia
    • +
    • Sscofpmf
    • +
    • Ssstateen
    • +
    • Sstc
    • +
    • Svinval
    • +
    • Svnapot
    • +
    • Svpbmt
    • +
    +
  • +
  • Support for the following vendor extensions has been added: +
      +
    • T-Head: +
        +
      • XTheadVector
      • +
      +
    • +
    • CORE-V: +
        +
      • XCVmac
      • +
      • XCValu
      • +
      • XCVelw
      • +
      • XCVsimd
      • +
      • XCVbi
      • +
      +
    • +
    • Ventana Micro: +
        +
      • XVentanaCondops
      • +
      +
    • +
    +
  • +
  • The following new CPUs are supported through the -mcpu + option (GCC identifiers in parentheses). +
      +
    • SiFive's X280 (sifive-x280).
    • +
    • SiFive's P450 (sifive-p450).
    • +
    • SiFive's P670 (sifive-p670).
    • +
    +
  • +
  • The following new CPUs are supported through the -mtune + option (GCC identifiers in parentheses). +
      +
    • Generic out-of-order core (generic-ooo).
    • +
    • SiFive's P400 series (sifive-p400-series).
    • +
    • SiFive's P600 series (sifive-p600-series).
    • +
    • XiangShan's Nanhu microarchitecture (xiangshan-nanhu).
    • +
    +
  • +
-- 2.34.1