From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by sourceware.org (Postfix) with ESMTPS id 782D73858D33 for ; Sat, 20 Apr 2024 01:12:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 782D73858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 782D73858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713575532; cv=none; b=OaOS8jZg4zvkZxpDx35norN77KJoN5kwBGHhJdeoCWGeOqbU7mcKZWULF8Rphf+EcgRLWqcb6bPIuP466UZkoFseUBrEZofl1iBBMMA+xsbdS2xsWlHgq99LTaq681i8/OUbs42uOeA3FalaFKp27vjbAjKdAg/q6DZ0N3Vb8YE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713575532; c=relaxed/simple; bh=60oh2FhhJxL03ni/SU8eMmrtI8IIFH++rzchASPURgY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=h7b/JQ7LUOoGjYMi8hJVMw2IFu6Jsbie23ek8yNotMeZhmNzQCyn/Rz44savgC5qnnpZcuArmaZVRS3yuHNgyste2D84oIP4d08AbbFX5s607pUqbRGh+XKZRKhr+4jqNK0YaoAsnJHh5ZN1+BwPif0DRrMR6ciGPOUOj28t7XA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713575528; x=1745111528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=60oh2FhhJxL03ni/SU8eMmrtI8IIFH++rzchASPURgY=; b=WBLkXpR+UCOfoCyGei/MOpPpQzpmEpFxf90kd8M1Zs1buSWyPaU46GE1 EzH/UgGLy1f2ychESgFutL2x/oUOZH6h4J8+W/NdPMj7RPnwZiEMrziGg pTQFmbZSlpaPeGqGJtoapWBBavo+mt51xDbatjP/CT+0kob88EdpQnLXp RxQzmX9uuNWGkunHR1JANYc0Bu3QoKCTuwXmlEyneOACqqsNJHuAM/qoj gbEd0GVSl8IEFNLv4snYXAQvXWSx/rZgB1GQF8u1xM9yphTSN6rpeo2Ib 1zTj6p1VsiRRt9lvC5Y2m1URhFFnDHx2j+fAIiqnhtyIrOZCijbAUsFng w==; X-CSE-ConnectionGUID: TQcseYI7Qsut7ztPkd8DbA== X-CSE-MsgGUID: D8ppk5mPTIC98RsU7AoNfg== X-IronPort-AV: E=McAfee;i="6600,9927,11049"; a="9058851" X-IronPort-AV: E=Sophos;i="6.07,215,1708416000"; d="scan'208";a="9058851" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2024 18:12:07 -0700 X-CSE-ConnectionGUID: B2JEK+SiSyyTovExU3w97A== X-CSE-MsgGUID: FQnuCksxQx+dLzK7T90PPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,215,1708416000"; d="scan'208";a="28153307" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa004.fm.intel.com with ESMTP; 19 Apr 2024 18:12:07 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 2EDAD100567A; Sat, 20 Apr 2024 09:12:06 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v2] RISC-V: Add xfail test case for wv insn register overlap Date: Sat, 20 Apr 2024 09:12:05 +0800 Message-Id: <20240420011205.2025920-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240420010454.2019265-1-pan2.li@intel.com> References: <20240420010454.2019265-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li We reverted below patch for wv insn overlap, add the related wv insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. b3b2799b872 RISC-V: Support one more overlap for wv instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-42.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-42.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c new file mode 100644 index 00000000000..fa5dac58a20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */ + +#include + +int64_t +reduc_plus_int (int *__restrict a, int n) +{ + int64_t r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +double +reduc_plus_float (float *__restrict a, int n) +{ + double r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */ -- 2.34.1