From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by sourceware.org (Postfix) with ESMTPS id 4D5DC385840D for ; Wed, 24 Apr 2024 12:59:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4D5DC385840D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4D5DC385840D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713963548; cv=none; b=lJeid2COPEhZf1g+2g8/bWgyjBVsv/MpTL13TKeYdcsx5oWtWVqFZA+kxRcZqdeRrl4Kxhw+M7DFmSk1NEzxjEH54wjxH9+xlVb1s+EcG0SMN2pBFzYLn0GpcJdA5SNxHdoqSpmtt6mpdpGAyoggKDL3IGGaI2tR0WQbxjMcLu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713963548; c=relaxed/simple; bh=by82+jYxrJZ8V8gOZPntgZ7HQsBJ6PdQ41VV8df+l3o=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ILAt9xq+qN1LXQZRdc9RuzeXxzY3TX1hLJLKTML+yW5xJdHOEVD7qJjX9MF+csyqIXlvttFJOy1AHZR2Uj5OX8h9iNB+AvJXcR5f+FLisDWTyuhnBqa40v2jsk+abCsO88Jbt+4z8yO+IPKNhpALFuTQOL7zksuq4Nit/r4LsiE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713963546; x=1745499546; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=by82+jYxrJZ8V8gOZPntgZ7HQsBJ6PdQ41VV8df+l3o=; b=LgPrqtUIG7lLkoGQEzCHLxqCUl8JCMOncu8bzMX+WRW5TSUypYmQEOVx LFXS6wsM8arMe60r7dqm6ww8gd5YKkO5TCdNboZX3qN+KcVdqIPwgispW eZVpcKg9WxfxPGe57awiTpzxquO6QGrCeSeMWSwXcBwTdnj1kOpAhOcSu t/N3lt8g2OvoEhqAoj4L6Px2N4urpBtlojrE7vhjG14cC/CG18AWCcyRt G9CqeOVypuOy7NZSkxZUc+FaKaSubspURCRYa3gm35kRr0AB5JsQdHyG5 HB7Qb0lT1Wx+LQczcX4/0Uzb4nYoQO8j3D78HGOFlBdC5eQS4ISNXu1C8 w==; X-CSE-ConnectionGUID: a63IouZmQ8y/R+bxOteQTg== X-CSE-MsgGUID: mqP7QejeSCCzDFafjkEG5Q== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9521677" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9521677" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 05:59:04 -0700 X-CSE-ConnectionGUID: 9J8tGWHGS9etyQ1+iUzXZQ== X-CSE-MsgGUID: +2wdIWhwRG+5w/yExF5lXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29502030" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa005.jf.intel.com with ESMTP; 24 Apr 2024 05:59:02 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A19A51010203; Wed, 24 Apr 2024 20:59:01 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] Revert "RISC-V: Support highpart register overlap for vwcvt" Date: Wed, 24 Apr 2024 20:58:59 +0800 Message-Id: <20240424125859.994208-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SCC_10_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This reverts commit bdad036da32f72b84a96070518e7d75c21706dc2. --- gcc/config/riscv/constraints.md | 23 ---- gcc/config/riscv/riscv.md | 24 ---- gcc/config/riscv/vector-crypto.md | 21 ++-- gcc/config/riscv/vector.md | 19 ++-- .../gcc.target/riscv/rvv/base/pr112431-1.c | 104 ------------------ .../gcc.target/riscv/rvv/base/pr112431-2.c | 68 ------------ .../gcc.target/riscv/rvv/base/pr112431-3.c | 51 --------- .../gcc.target/riscv/rvv/base/pr112431-39.c | 2 +- .../gcc.target/riscv/rvv/base/pr112431-40.c | 2 +- .../gcc.target/riscv/rvv/base/pr112431-41.c | 2 +- 10 files changed, 22 insertions(+), 294 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index e37c6936bfa..a590df545d7 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -159,29 +159,6 @@ (define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS" (define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS" "A vector mask register (if available).") -;; These following constraints are used by RVV instructions with dest EEW > src EEW. -;; RISC-V 'V' Spec 5.2. Vector Operands: -;; The destination EEW is greater than the source EEW, the source EMUL is at least 1, -;; and the overlap is in the highest-numbered part of the destination register group. -;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not). -(define_register_constraint "W21" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 2 == 1." "regno % 2 == 1") - -(define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 == 2." "regno % 4 == 2") - -(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 4." "regno % 8 == 4") - -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 == 1." "regno % 4 == 1") - -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 1." "regno % 8 == 1") - -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 2." "regno % 8 == 2") - ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". ;; VLENB is a run-time constant which represent the vector register length in bytes. ;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1693d4008c6..455715ab2f7 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -538,27 +538,6 @@ (define_attr "fp_vector_disabled" "no,yes" ] (const_string "no"))) -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" - (const_string "no")) - -(define_attr "vconstraint_enabled" "no,yes" - (cond [(eq_attr "vconstraint" "no") - (const_string "yes") - - (and (eq_attr "vconstraint" "W21") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2")) - (const_string "no") - - (and (eq_attr "vconstraint" "W42,W41") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4")) - (const_string "no") - - (and (eq_attr "vconstraint" "W84,W81,W82") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8")) - (const_string "no") - ] - (const_string "yes"))) - ;; This attribute marks the alternatives not matching the constraints ;; described in spec as disabled. (define_attr "spec_restriction" "none,thv,rvv" @@ -587,9 +566,6 @@ (define_attr "enabled" "no,yes" (eq_attr "fp_vector_disabled" "yes") (const_string "no") - (eq_attr "vconstraint_enabled" "no") - (const_string "no") - (eq_attr "spec_restriction_disabled" "yes") (const_string "no") ] diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md index 23dc549e5b8..8a4888a7653 100755 --- a/gcc/config/riscv/vector-crypto.md +++ b/gcc/config/riscv/vector-crypto.md @@ -303,26 +303,25 @@ (define_insn "@pred_vwsll" (set_attr "mode" "")]) (define_insn "@pred_vwsll_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1, vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (ashift:VWEXTI (zero_extend:VWEXTI - (match_operand: 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, rK")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_ZVBB" "vwsll.v%o4\t%0,%3,%4%p1" [(set_attr "type" "vwsll") - (set_attr "mode" "") - (set_attr "vconstraint" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,no,no")]) + (set_attr "mode" "")]) ;; vbrev.v vbrev8.v vrev8.v (define_insn "@pred_v" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6a4c0e6e10f..228d0f9a766 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3945,22 +3945,22 @@ (define_insn "@pred_widen_mulsu_scalar" ;; vwcvt.x.x.v (define_insn "@pred_" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" " vr, vr")) (vec_duplicate:VWEXTI (reg: X0_REGNUM))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwcvt.x.x.v\t%0,%3%p1" [(set_attr "type" "viwalu") @@ -3968,8 +3968,7 @@ (define_insn "@pred_" (set_attr "vl_op_idx" "4") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7)) - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set (attr "avl_type_idx") (const_int 7))]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c deleted file mode 100644 index 6b9a7c448f0..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c +++ /dev/null @@ -1,104 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 = __riscv_vwcvt_x_x_v_i16m2 (v0, vl); - vint16m2_t vw1 = __riscv_vwcvt_x_x_v_i16m2 (v1, vl); - vint16m2_t vw2 = __riscv_vwcvt_x_x_v_i16m2 (v2, vl); - vint16m2_t vw3 = __riscv_vwcvt_x_x_v_i16m2 (v3, vl); - vint16m2_t vw4 = __riscv_vwcvt_x_x_v_i16m2 (v4, vl); - vint16m2_t vw5 = __riscv_vwcvt_x_x_v_i16m2 (v5, vl); - vint16m2_t vw6 = __riscv_vwcvt_x_x_v_i16m2 (v6, vl); - vint16m2_t vw7 = __riscv_vwcvt_x_x_v_i16m2 (v7, vl); - vint16m2_t vw8 = __riscv_vwcvt_x_x_v_i16m2 (v8, vl); - vint16m2_t vw9 = __riscv_vwcvt_x_x_v_i16m2 (v9, vl); - vint16m2_t vw10 = __riscv_vwcvt_x_x_v_i16m2 (v10, vl); - vint16m2_t vw11 = __riscv_vwcvt_x_x_v_i16m2 (v11, vl); - vint16m2_t vw12 = __riscv_vwcvt_x_x_v_i16m2 (v12, vl); - vint16m2_t vw13 = __riscv_vwcvt_x_x_v_i16m2 (v13, vl); - vint16m2_t vw14 = __riscv_vwcvt_x_x_v_i16m2 (v14, vl); - vint16m2_t vw15 = __riscv_vwcvt_x_x_v_i16m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c deleted file mode 100644 index da92d59406f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m4_t vw0 = __riscv_vwcvt_x_x_v_i16m4 (v0, vl); - vint16m4_t vw1 = __riscv_vwcvt_x_x_v_i16m4 (v1, vl); - vint16m4_t vw2 = __riscv_vwcvt_x_x_v_i16m4 (v2, vl); - vint16m4_t vw3 = __riscv_vwcvt_x_x_v_i16m4 (v3, vl); - vint16m4_t vw4 = __riscv_vwcvt_x_x_v_i16m4 (v4, vl); - vint16m4_t vw5 = __riscv_vwcvt_x_x_v_i16m4 (v5, vl); - vint16m4_t vw6 = __riscv_vwcvt_x_x_v_i16m4 (v6, vl); - vint16m4_t vw7 = __riscv_vwcvt_x_x_v_i16m4 (v7, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c deleted file mode 100644 index 46f93a9049b..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m8_t vw0 = __riscv_vwcvt_x_x_v_i16m8 (v0, vl); - vint16m8_t vw1 = __riscv_vwcvt_x_x_v_i16m8 (v1, vl); - vint16m8_t vw2 = __riscv_vwcvt_x_x_v_i16m8 (v2, vl); - vint16m8_t vw3 = __riscv_vwcvt_x_x_v_i16m8 (v3, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c index 770b5411666..1234718bb35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c @@ -155,4 +155,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c index f044a504fc8..5d6577cfe6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c @@ -91,4 +91,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c index 6bdcac82ea8..c31144c05b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c @@ -59,4 +59,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ -- 2.34.1